SH7243 datasheet(295/1726 Pages) RENESAS

Part #	SH7243

Description	Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine family

PDF	1726 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

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295 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 265 of 1692

REJ09B0393-0100

Bit

Bit Name

Initial

Value

R/W

Description

BAS*

R/W

Byte Access Selection when SRAM with Byte

Selection is Used

Specifies the

WEn and RD/WR signal timing when the

SRAM interface with byte selection is used.

0: Asserts the

WEn signal at the read/write timing and

asserts the RD/

WR signal during the write access

cycle.

1: Asserts the

WEn signal during the read/write access

cycle and asserts the RD/

WR signal at the write

timing.

19 to 13

 *

All 0

R/W

Reserved

Set these bits to 0 when the interface for normal space

or SRAM with byte selection is used.

12, 11

SW[1:0]

R/W

Number of Delay Cycles from Address,

CS0 Assertion

RD, Wen Assertion

Specify the number of delay cycles from address and

CS0 assertion to RD and Wen assertion.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

SH7243 Datasheet(PDF) 295 Page - Renesas Technology Corp

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