SH7243 datasheet(299/1726 Pages) RENESAS

299 / 1726 page

Section 9 Bus State Controller (BSC)

Rev. 1.00 Jun. 26, 2008 Page 269 of 1692

REJ09B0393-0100

Bit

Bit Name

Initial

Value

R/W

Description

10 to 7

WR[3:0]

1010

R/W

Number of Read Access Wait Cycles

Specify the number of cycles that are necessary for

read access.

0000: No cycle

0001: 1 cycle

0010: 2 cycles

0011: 3 cycles

0100: 4 cycles

0101: 5 cycles

0110: 6 cycles

0111: 8 cycles

1000: 10 cycles

1001: 12 cycles

1010: 14 cycles

1011: 18 cycles

1100: 24 cycles

1101: Reserved (setting prohibited)

1110: Reserved (setting prohibited)

1111: Reserved (setting prohibited)

R/W

External Wait Mask Specification

Specifies whether or not the external wait input is valid.

The specification by this bit is valid even when the

number of access wait cycle is 0.

0: External wait input is valid

1: External wait input is ignored

5 to 2



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

1, 0

HW[1:0]

R/W

Delay Cycles from RD,

WEn Negation to Address, CSn

Negation

Specify the number of delay cycles from RD and

WEn

negation to address and

CSn negation.

00: 0.5 cycles

01: 1.5 cycles

10: 2.5 cycles

11: 3.5 cycles

SH7243 Datasheet(PDF) 299 Page - Renesas Technology Corp

SH7243 Datasheet(HTML) 299 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL