7540 datasheet(211/366 Pages) RENESAS

211 / 366 page

2-135

REJ09B0018-0200Z

Rev.2.00

Jun 21, 2004

7540 Group

APPLICATION

2.9 Reset

2.9 Oscillation control

This paragraph explains the registers setting method and the notes relevant to the oscillation control.

2.9.1 Memory map

Fig. 2.9.1 Memory map of registers relevant to oscillation control

2.9.2 Relevant registers

003816

003916

003B16

MISRG

Watchdog timer control register (WDTCON)

CPU mode register (CPUM)

Fig. 2.9.2 Structure of MISRG

b7 b6 b5 b4 b3 b2 b1 b0

Function

At reset

Name

MISRG [Address : 3816]

Nothing is allocated for these bits. These are write disabled bits.

When these bits are read out, the values are “0”.

MISRG

Oscillation stabilization time

set bit after release of the

STP instruction

0 : Set “0116” in timer 1, and

“FF16” in prescaler 1

automatically

1 : Not set automatically

These are reserved bits.

Do not write “1” to these bits.

(Note)

0 : Oscillation stop not detected

1 : Oscillation stop detected

Ceramic or RC oscillation stop

detection function active bit

0 : Detection function inactive

1 : Detection function active

Oscillation stop detection

status bit

Note: “0” at normal reset

“1” at reset by detecting the oscillation stop

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