7733 datasheet(474/940 Pages) RENESAS

474 / 940 page

LOW VOLTAGE VERSION

7733 Group User’s Manual

18–8

18.4 Electrical characteristics

18.4.2 Recommended operating conditions

Recommended operating conditions (Vcc = 2.7 to 5.5 V, Ta = –40 to 85

°C, unless otherwise noted)

MHz

kHz

Power source voltage

Analog power source voltage

Power source voltage

Analog power source voltage

High-level input voltage

Low-level input voltage

High-level peak output current

High-level average output current

Low-level peak output current

Low-level average output current

Main-clock oscillation frequency (Note 4)

Sub-clock oscillation frequency

f(XIN) :Operating

f(XIN) :Stopped, f(XCIN) = 32.768 kHz

P00–P07, P30–P33, P40–P47,

P50–P57, P60–P67, P70–P77,

P80–P87, XIN, RESET, CNVss,

BYTE, XCIN (Note 3)

P10–P17, P20–P27

(in single-chip mode)

P10–P17, P20–P27

(in memory expansion mode and

microprocessor mode)

P00–P07, P30–P33, P40–P47,

P50–P57, P60–P67, P70–P77,

P80–P87, XIN, RESET, CNVss,

BYTE, XCIN (Note 3)

P10–P17, P20–P27

(in single-chip mode)

P10–P17, P20–P27

(in memory expansion mode and

microprocessor mode)

P00–P07, P10–P17, P20–P27,

P30–P33, P40–P47, P50–P57,

P60–P67, P70–P77, P80–P87

P00–P07, P10–P17, P20–P27,

P30–P33, P40–P47, P50–P57,

P60–P67, P70–P77, P80–P87

P00–P07, P10–P17, P20–P27,

P30–P33, P40–P43, P54–P57,

P60–P67, P70–P77, P80–P87

P44–P47, P50–P53

P00–P07, P10–P17, P20–P27,

P30–P33, P40–P43, P54–P57,

P60–P67, P70–P77, P80–P87

P44–P47, P50–P53

Vcc

AVcc

Vss

AVss

VIH

VIL

IOH (peak)

IOH (avg)

IOL (peak)

IOL (avg)

f(XIN)

f(XCIN)

Parameter

Symbol

Limits

Min.

Max.

5.5

2.7

Vcc

32.768

Typ.

Unit

0.8 Vcc

Vcc

0.2 Vcc

0.16 Vcc

–10

–5

0.5 Vcc

Notes 1: Average output current is the average value of an interval of 100 ms.

2: The sum of IOL(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less,

the sum of IOH(peak) for ports P0, P1, P2, P3, and P8 must be 80 mA or less,

the sum of IOL(peak) for ports P4, P5, P6, and P7 must be 100 mA or less, and

the sum of IOH(peak) for ports P4, P5, P6, and P7 must be 80 mA or less.

3: Limits VIH and VIL for XCIN are applied when the sub clock external input selection bit = “1.”

4: The maximum value of f(XIN) = 6 MHz when the main clock division selection bit = “1.”

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