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CENTRAL PROCESSING UNIT (CPU)

7733 Group User’s Manual

2–9

(5) Bit 4: Index register length flag (x)

This flag determines whether index register X or index register Y is used as a 16-bit register or an

8-bit register. The register is used as a 16-bit register when this flag is “0” and as an 8-bit register

when this flag is “1.” When setting this flag to “1,” execute the SEP instruction; when clearing this flag

to “0,” execute the CLP instruction.

At reset, this flag is cleared to “0.”

Note: When data is transferred between registers which are different in bit length, the data is transferred

with the bit length of the destination register. But this is not applied to the case where the TXA,

TYA, TXB, or TYB instruction is executed. Refer to “7700 Family Software Manual” for

details.

(6) Bit 5: Data length flag (m)

This flag determines whether data is used as 16-bit data or 8-bit data. Data is used as 16-bit data

when this flag is “0” and as 8-bit data when this flag is “1.” When setting this flag to “1,” execute the

SEM or SEP instruction; when clearing this flag to “0,” execute the CLM or CLP instruction.

At reset, this flag is cleared to “0.”

Note: When data is transferred between registers which are different in bit length, the data is transferred

with the data length of the destination register. But this is not applied to the case where the

TXA, TYA, TXB, or TYB instruction is executed. Refer to “7700 Family Software Manual” for

details.

(7) Bit 6: Overflow flag (V)

This flag is valid when addition or subtraction is executed for each word which is processed as signed

binary data. If the data length flag (m) is “0,” the overflow flag is set to “1” when the result of addition

or subtraction exceeds the range between –32768 and +32767 and cleared to “0” in the other cases.

If the data length flag (m) is “1,” the overflow flag is set to “1” when the result of addition or subtraction

exceeds the range between –128 and +127 and cleared to “0” in the other cases. Also, the overflow

flag is set to “1” when the length of the division result obtained by the DIV instruction is longer than

that of a register where the result is to be stored. When the BVC or BVS instruction is executed, the

program branches according to this flag’s state. This flag is ignored in the decimal mode. When setting

this flag to “1,” execute the SEP instruction; when clearing this flag to “0,” execute the CLV or CLP

instruction.

(8) Bit 7: Negative flag (N)

This flag is set to “1” when the result of an arithmetic operation or data transfer is negative. (Bit 15

of the result is “1” when the data length flag (m) is “0,” or bit 7 of the result is “1” when the data length

flag (m) is “1.”) It is cleared to “0” in the other cases. When the BPL or BMI instruction is executed,

the program branches according to this flag’s state. This flag is ignored in the decimal mode. When

setting this flag to “1,” execute the SEP instruction; when clearing this flag to “0,” execute the CLP

instruction.

(9) Bits 8 to 10: Processor interrupt priority level (IPL)

These bits can specify one of levels 0 to 7 as the processor interrupt priority level. An interrupt is

enabled when its interrupt priority level, which is set in the interrupt control register, is higher than IPL.

When the interrupt request is accepted, the contents of IPL is stored into the stack area and the

interrupt priority level of the accepted interrupt is set in IPL.

No instruction can directly set or clear each of these bits. When changing these bits, store a desired

processor interrupt priority level into the stack area. And then, change the contents of the processor

status register by executing the PUL or PLP instruction.

At reset, the contents of IPL is cleared to “0002.”

2.1 Central processing unit

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