7733 datasheet(12/940 Pages) RENESAS

12 / 940 page

7733 Group User’s Manual

Table of contents

10.2 Operation description ....................................................................................................... 10-5

10.2.1 Basic operation ........................................................................................................... 10-5

10.2.2 Operation in stop mode ............................................................................................. 10-6

10.2.3 Operation in wait mode ............................................................................................. 10-7

10.2.4 Operation in hold state .............................................................................................. 10-8

10.3 Precautions for watchdog timer ................................................................................... 10-10

CHAPTER 11. STOP AND WAIT MODES

11.1 Overview .............................................................................................................................. 11-2

11.2 Clock generating circuit ................................................................................................... 11-3

11.3 Stop mode ........................................................................................................................... 11-6

11.3.1 Output levels of external bus and bus control signals in stop mode ................. 11-7

11.3.2 Stop mode terminating operation by interrupt request occurrence (when using watchdog timer) 11-9

11.3.3 Stop mode terminating operation by interrupt request occurrence (when not

using watchdog timer) .............................................................................................. 11-10

11.3.4 Stop mode terminating operation by hardware reset .......................................... 11-12

11.3.5 Precautions for stop mode ......................................................................................11-12

11.4 Wait mode .......................................................................................................................... 11-13

11.4.1 State of clocks f2 to f512 in wait mode ................................................................ 11-15

11.4.2 Output levels of external bus and bus control signals in wait mode ............... 11-15

11.4.3 Wait mode terminating operation by interrupt request occurrence ................... 11-17

11.4.4 Wait mode terminating operation by hardware reset .......................................... 11-17

CHAPTER 12. CONNECTING EXTERNAL DEVICES

12.1 Signals required for accessing external devices ...................................................... 12-2

12.1.1 External bus (A0 to A7, A8/D8 to A15/D15, and A16/D0 to A23/D7) ..................... 12-5

12.1.2 External data bus width selection signal (Pin BYTE’s level) ................................ 12-6

12.1.3 Enable signal (E) ........................................................................................................ 12-6

12.1.4 Read/Write signal (R/W) ............................................................................................ 12-6

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12.1.5 Byte high enable signal (BHE) ................................................................................. 12-7

12.1.6 Address latch enable signal (ALE) ...........................................................................12-7

____

12.1.7 Signal related to ready function (RDY) .................................................................. 12-7

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12.1.8 Signals related to hold function (HOLD, HLDA) .................................................... 12-7

12.1.9 Clock

φ1 ....................................................................................................................... 12-7

12.1.10 Operation of bus interface unit (BIU) ................................................................. 12-10

12.2 Software wait .................................................................................................................... 12-13

12.3 Ready function ................................................................................................................. 12-16

12.3.1 Operation in ready state .......................................................................................... 12-17

12.4 Hold function .................................................................................................................... 12-19

12.4.1 Operation in hold state .......................................................................................... 12-20

CHAPTER 13. RESET

13.1 Hardware reset ................................................................................................................... 13-2

13.1.1 Pin state ...................................................................................................................... 13-3

13.1.2 State of CPU, SFR area, and internal RAM area ................................................. 13-4

13.1.3 Internal processing sequence after a reset ........................................................... 13-9

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13.1.4 Time required for applying “L” level to pin RESET ............................................ 13-10

13.2 Software reset ................................................................................................................... 13-12

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