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7733 Datasheet(PDF) 90 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 90 Page - Renesas Technology Corp |
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90 / 940 page  7733 Group User's Manual 4–11 INTERRUPTS A-D/UART2 trans./rece. UART1 transmission UART1 reception UART0 transmission UART0 reception Timer B2 Timer B1 Timer B0 Timer A4 Timer A3 Timer A2 Timer A1 Timer A0 INT2/Key input INT1 INT0 IPL Processor interrupt priority level Interrupt with the highest priority Interrupt disable flag (I) Watchdog timer interrupt Reset Interrupt request is accepted. Interrupt priority level of each interrupt Level 0 (Initial value) Interrupt priority level of each interrupt 4.5 Interrupt priority level detection circuit The interrupt priority level detection circuit is used to select an interrupt with the highest priority from multiple interrupts which reside at the same sampling timing. Figure 4.5.1 shows the interrupt priority level detection circuit. 4.5 Interrupt priority level detection circuit Fig. 4.5.1 Interrupt priority level detection circuit |
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