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7733 Datasheet(PDF) 480 Page - Renesas Technology Corp

Part # 7733
Description  16-BIT SINGLE-CHIP MICROCOMPUTER
PDF  940 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7733 Datasheet(HTML) 480 Page - Renesas Technology Corp

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LOW VOLTAGE VERSION
7733 Group User’s Manual
18–14
18.4 Electrical characteristics
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min.
666
333
333
Max.
Min.
666
333
333
Timer B input (Count input in event counter mode)
tc(TB)
tw(TBH)
tw(TBL)
tc(TB)
tw(TBH)
tw(TBL)
Min.
Max.
ns
ns
ns
ns
ns
ns
Limits
Unit
Symbol
TBiIN input cycle time
TBiIN input high-level pulse width
TBiIN input low-level pulse width
tc(TB)
tw(TBH)
tw(TBL)
ns
ns
ns
Limits
Unit
Symbol
Parameter
Timer B input (Pulse period measurement mode)
Parameter
TBiIN input cycle time (One edge count)
TBiIN input high-level pulse width (One edge count)
TBiIN input low-level pulse width (One edge count)
TBiIN input cycle time (Both edges count)
TBiIN input high-level pulse width (Both edges count)
TBiIN input low-level pulse width (Both edges count)
250
125
125
500
250
250
Timer B input (Pulse width measurement mode)
tc(TB)
tw(TBH)
tw(TBL)
TBiIN input cycle time
TBiIN input high-level pulse width
TBiIN input low-level pulse width
Limits
Unit
Symbol
Parameter
Max.
ADTRG
input cycle time (Minimum allowable trigger)
ADTRG
input low-level pulse width
Min.
Max.
ns
ns
Limits
Unit
Parameter
Symbol
tc(AD)
tw(ADL)
A-D trigger input
1333
166
Serial I/O
CLKi input cycle time
CLKi input high-level pulse width
CLKi input low-level pulse width
TxDi output delay time
TxDi hold time
RxDi input setup time
RxDi input hold time
tc(CK)
tw(CKH)
tw(CKL)
td(C–Q)
th(C–Q)
tsu(D–C)
th(C–D)
Min.
Max.
100
Limits
Unit
Symbol
Parameter
333
166
166
0
65
75
Data formula (Min.)
Data formula (Min.)
8 ! 109
2!
f(f2)
4 ! 109
2!
f(f2)
4 ! 109
2!
f(f2)
(Note 2)
(Note 2)
(Note 2)
Notes 1: The TBiIN input cycle time must be 4 cycles of a count source or more.
The TBiIN input high-level pulse width and low-level pulse width must be 2 cycles of a count source
or more, respectively.
2: f(f2) represents the clock f2 frequency.
For the relationship with the main clock and sub clock, refer to Table 14.3.1.
8 ! 109
2!
f(f2)
4 ! 109
2!
f(f2)
4 ! 109
2!
f(f2)



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