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7733 Datasheet(PDF) 564 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 564 Page - Renesas Technology Corp |
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564 / 940 page ![]() APPENDIX 7733 Group User’s Manual 21-16 Appendix 3. Control registers UARTi transmit/receive control register 1 At reset Bit Bit name 5 Framing error flag (Notes 1 and 2) (Valid in the UART mode.) 0 0: No framing error is detected. 1: Framing error is detected. RW Functions b7 b6 b5 b4 b3 b2 b1 b0 UART0 transmit/receive control register 1 (address 3516) UART1 transmit/receive control register 1 (address 3D16) UART2 transmit/receive control register 1 (address 6916) Notes 1: Bits 4 to 7 are cleared to “0” when the serial I/O mode selection bits (bits 2 to 0 at addresses 3016, 3816) are cleared to “0002” or when the receive enable bit is cleared to “0.” (Bit 7 is cleared to “0” when all of bits 4 to 6 are “0.”) Note also that bits 5 and 6 are cleared to “0” when the low-order byte of the UARTi receive buffer register (addresses 3616, 3E16, 6A16) is read out. 2: Bits 5 to 7 are ignored in the clock synchronous serial I/O mode. 0 Transmit enable bit 0 0: Transmission is disabled. 1: Transmission is enabled. 1 Transmission buffer empty flag 1 0: Data is present in the transmission buffer register. 1: No data is present in the transmission buffer register. 2 Receive enable bit 0 0: Reception is disabled. 1: Reception is enabled. 3 Receive completion flag 0 0: No data is present in the receive buffer register. 1: Data is present in the receive buffer register. 4 Overrun error flag (Note 1) 0 0: No overrun error is detected. 1: Overrun error is detected. 6 Parity error flag (Notes 1 and 2) (Valid in the UART mode.) 0 0: No parity error is detected. 1: Parity error is detected. 7 Error sum flag (Notes 1 and 2) (Valid in the UART mode.) 0 0: No error is detected. 1: Error is detected. RW RO RW RO RO RO RO RO UARTi receive buffer register b7 b0 (b15) (b8) b7 b0 UART0 receive buffer register (addresses 3716, 3616) UART1 receive buffer register (addresses 3F16, 3E16) UART2 receive buffer register (addresses 6B16, 6A16) Bit Not implemented. A value of “0” is read out from here. The receive data is read out from here. At reset 0 Un- defined RW Functions 8 to 0 15 to 9 RO — |
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