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7733 Datasheet(PDF) 583 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 583 Page - Renesas Technology Corp |
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583 / 940 page  APPENDIX 7733 Group User’s Manual 21-35 Appendix 3. Control registers Serial transmit control register Bit Bit name At reset RW Functions b7 b6 b5 b4 b3 b2 b1 b0 Serial transmit control register (address 6E16) g When using multiple transfer clock output pins, satisfy the following conditions: q Serial I/O mode selection bits (bits 2 to 0 at address 3016) = “0012” q Internal/external clock selection bit (bit 3 at address 3016) = “0” q CTS/RTS enable bit (bit 4 at address 3416) = “1” q Receive enable bit (bit 2 at address 3516) = “0” (for cases and in Table 8.3.4) q Transmission clock output pin selection bits = “012”, “102”, or “112” (Refer to Table 8.3.3.) Note: Bits 4 and 5 are ignored in the UART mode. (They may be “0” or “1.”) Not implemented. Un- defined 4 Transmission clock output pin selection bits (Valid only in the clock synchronous serial I/O mode.) (Note) 0 0 0: One transfer clock output pin (CLK0) 0 1: 1 0: 1 1: 5 0 0 3 to 0 7, 6 Not implemented. Value “0” is read out from here. b5 b4 Multiple transfer clock output pins — RW RW — |
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