7733 datasheet(637/940 Pages) RENESAS

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OVERVIEW

1–5

7735 Group User’s Manual

Input/Output

I/O

Output

I/O

Output

P00–P07

_______

CS0

–CS4,

_____

RSMP

, A16, A17

P20–P27

A0/D0–

A7/D7

P30–P33

________

WEL

________

WEH

ALE,

_____

HLDA

Table 1.3.2 Pin description (2)

Functions

[Single-chip Mode]

Same as the 7733 Group.

[Memory Expansion Mode] [Microprocessor Mode]

_______

____________

These pins respectively output signals CS0–CS4, RSMP,

and address’s high-order 2 bits (A16 and A17).

_______

q Signal CS0–CS4

These signals are the chip select signals. When the microcomputer

accesses a certain area, the corresponding pin outputs “L” level.

(Refer to Table 2.5.3.)

____________

q Signal RSMP

This signal is the ready sampling signal and is used

________

to generate signal RDY for accessing external memory

area.

[Single-chip Mode]

Same as the 7733 Group.

[Memory Expansion Mode] [Microprocessor Mode]

Input/Output of data (D0–D7) and output of address’s

low-order 8 bits (A0–A7) are performed with the time

sharing method.

[Single-chip Mode]

Same as the 7733 Group.

[Memory Expansion Mode] [Microprocessor Mode]

________

_________

These pins respectively output signals WEL, WEH , ALE,

_____

and HLDA.

________

_________

q Signal WEL, WEH

____

Signal WEL is the write enable low signal.

____

Signal WEH is the write enable high signal.

These signals’ levels are “L” in the data write period

of the write cycle.

The operations of these signals depend on the level

of pin BYTE. (Refer to Table 12.1.1.)

q Signal ALE

This signal is used to separate the multiplexed signal

which consists of an address and data to the address

and the data.

_____

q Signal HLDA

This signal informs the external whether the

microcomputer enters the Hold state or not.

__________

In Hold state, pin HLDA outputs “L” level.

Name

I/O port P0

I/O port P2

I/O port P3

1.3 Pin description

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