7733 datasheet(649/940 Pages) RENESAS

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CENTRAL PROCESSING UNIT (CPU)

7735 Group User’s Manual

2–9

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2.5.4 Relationship between access addresses and chip select signals CS0 to CS4

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Table 2.5.3 lists the relationship between access addresses and chip select signals CS0 to CS4.

Table 2.5.4 lists the relationship between the memory allocation selection bits and addresses for chip

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select signals CS0, CS1 in the memory expansion mode.

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Table 2.5.3 Relationship between access addresses and chip select signals CS0 to CS4

2.5 Processor modes

Chip select

signal

_______

CS0

_______

CS1

_______

CS2

_______

CS3

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CS4

Microprocessor mode

00 100016

00 7FFF16

00 800016

03 FFFF16

04 000016

07 FFFF16

08 000016

0B FFFF16

0C 000016

0F FFFF16

Area

The former half of bank 0016 except for internal

memory area

•The latter half of bank 0016 except for internal

memory area

•Banks 0116 to 0316

Banks 0416 to 0716

Banks 0816 to 0B16

Banks 0C16 to 0F16

Memory expansion mode

(Note)

02 000016 (Note)

03 FFFF16

04 000016

07 FFFF16

08 000016

0B FFFF16

0C 000016

0F FFFF16

Note: This applies when each of bits 1 and 0 of the memory allocation control register (address 6316) = “0.”

For details, refer to Table 2.5.4.

Table 2.5.4 Relationship between memory allocation selection bits and addresses for chip select

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signals CS0, CS1 in memory expansion mode

Access addresses

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CS1

02000016 to 03FFFF16

01000016 to 03FFFF16

Memory allocation selection bitsV

Memory allocation selection bitsV : Bits 0 to 2 of the memory allocation control register (address 6316)

Internal ROM area

00100016 to 01FFFF16

(124 Kbytes)

00200016 to 01FFFF16

(120 Kbytes)

00800016 to 01FFFF16

(96 Kbytes)

00800016 to 00FFFF16

(32 Kbytes)

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CS0

00100016 to 001FFF16

00100016 to 007FFF16

Access addresses

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