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7733 Datasheet(PDF) 717 Page - Renesas Technology Corp |
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7733 Datasheet(HTML) 717 Page - Renesas Technology Corp |
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717 / 940 page  ELECTRICAL CHARACTERISTICS 7735 Group User’s Manual 15–3 15.6 Ready and Hold Timing requirements (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz (Note), unless otherwise noted) 15.6 Ready and Hold g The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted. HOLD input setup time RDY input hold time HOLD input hold time Limits tsu(RDY–φ1) tsu(HOLD–φ1) th(φ1–RDY) th(φ1–HOLD) RDY input setup time Max. ns ns ns ns Min. Parameter Symbol Unit 55 55 0 0 Note: This is applied when the main clock division selection bit = “0” and f(f2) = 12.5 MHz. Switching characteristics (Vcc = 5 V ± 10 %, Vss = 0 V, Ta = –20 to 85 °C, f(XIN) = 25 MHz, unless otherwise noted) HLDA output delay time td(φ1–HLDA) ns Min. Max. 50 Limits Unit Conditions Parameter Fig. 15.11.1 in part 1 Symbol |
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