7733 datasheet(775/940 Pages) RENESAS

775 / 940 page

EXTERNAL ROM VERSION

7735 Group User’s Manual

20–5

Functions

To pin Vcc, apply 5 V±10% (When the main clock is

the system clock) or 2.7 V to 5.5 V (When the sub-

clock is the system clock). To pin Vss, apply 0 V.

Connect to pin Vcc.

The microcomputer is reset when “L” level is input to

this pin.

Pins XIN and XOUT are the I/O pins of the clock

generating circuit, respectively. Connect these pins via

a ceramic resonator or a quartz-crystal oscillator. When

an external clock is used, the clock should be input to

pin XIN, and pin XOUT should be left open.

____

This pin outputs read enable signal RDE. RDE’s level

is “L” in the data read period of the read cycle.

Input level to this pin determines whether the external

data bus has a 16-bit width or an 8-bit width. A 16-bit

width is selected when the level is “L,” and an 8-bit

width is selected when the level is “H.”

Power source input for the A-D converter. Connect to

pin Vcc.

Power source input for the A-D converter. Connect to

pin Vss.

This is the reference voltage input pin for the A-D

converter.

___

_____

These pins respectively output signals CS0–CS4, RSMP,

and high-order 2 bits (A16, A17) of address.

___

q Signals CS0–CS4

These signals are the chip-select signals. When the microcomputer

accesses a certain area, the corresponding pin outputs “L“ level.

(Refer to Figure 12.1.3.)

_____

q Signal RSMP

This signal is the ready sampling signal and is used

____

to generate signal RDY for accessing the external

memory area.

q When the external data bus width = 8 bits

(Pin BYTE is at “H” level)

Address’s middle-order 8 bits (A8–A15) are output.

q When the external bus width = 16 bits

(Pin BYTE pin is at “L” level)

Input/Output of data (D8–D15) and output of address’s

middle-order 8 bits (A8–A15) are performed with the

time sharing system.

Name

Power source input

CNVss

Reset input

Clock input

Clock output

Read enable output

External data bus width

selection input

Analog power source

input

Reference voltage input

Chip select output,

Ready sampling output,

Address (high-order)

output

Address (middle-order)

output/Data I/O

20.3 Pin description

Tables 20.3.1 and 20.3.2 list the pin description.

Table 20.3.1 Pin description (1)

Vcc, Vss

CNVss

______

RESET

XIN

XOUT

____

RDE

BYTE

AVcc

AVss

VREF

____

CS0

(P00)–

____

CS4

(P04),

______

RSMP

(P05),

A16 (P06),

A17 (P07)

A8/D8

(P10) –

A15/D15

(P17)

Input/Output

Input

Output

Input

Output

I/O

7733 Datasheet(PDF) 775 Page - Renesas Technology Corp

7733 Datasheet(HTML) 775 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL