7733 datasheet(798/940 Pages) RENESAS

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APPENDIX

7735 Group User’s Manual

21-10

Oscillation circuit control register 1

2: Because this bit is “1” at reset, clear this bit to “0” with the initial setting program after

reset.

3: The case where data “010101012” is written with the procedure shown below is not

included.

4: For the 7733 Group, refer to Figure 14.3.3 in part 1.

Bit

Bit name

Functions

At reset

Main clock division selection bit

Sub clock external input selection bit

Must be fixed to “0” in the one time PROM and EPROM versions (Notes 1 and 2).

Must be fixed to “0” (Note 3).

Clock prescaler reset bit

Undefined

Oscillation circuit control register 1 (address 6F16)

0: Sub-clock oscillation circuit is operating

by itself. Pin P76 functions as pin XCOUT.

Watchdog timer is used when

terminating stop mode.

1: Sub clock is input from the external.

Pin P76 functions as a programmable

I/O port. Watchdog timer is not used when

terminating stop mode.

—

Not implemented.

Notes 1: When writing to this register, follow the procedure shown below.

By writing “1” to this bit, clock prescaler is

initialized.

(Note 4)

Undefined

Main clock external input selection bit

0: Main clock is divided by 2.

1: Main clock is not divided by 2.

0: Main-clock oscillation circuit is operating by

itself. Watchdog timer is used when

terminating stop mode.

1: Main clock is input from the external.

Watchdog timer is not used when

terminating stop mode.

Must be fixed to “0” in the mask ROM and external ROM versions (Note 1).

(Note 1)

Write data “010101012.”(LDM instruction)

• When writing to bits 0 to 3

Write data “00000XXX2.” (LDM instruction)

Next instruction

(b2 to b0 in the above Figure)

Write data “8016.” (LDM instruction)

• When performing clock prescaler reset

Appendix 3. Control registers

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