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7733 Datasheet(PDF) 903 Page - Renesas Technology Corp

Part # 7733
Description  16-BIT SINGLE-CHIP MICROCOMPUTER
PDF  940 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

7733 Datasheet(HTML) 903 Page - Renesas Technology Corp

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LOW VOLTAGE VERSION
7736 Group User’s Manual
18–11
18.4 Electrical characteristics
18.4.7 Single-chip mode
Timing requirements (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note 1), unless
otherwise noted)
g The rise/fall time of an input signal must be 100 ns or less, unless otherwise noted.
tc
tw(H)
tw(L)
tr
tf
tsu(P0D–E)
tsu(P1D–E)
tsu(P2D–E)
tsu(P3D–E)
tsu(P4D–E)
tsu(P5D–E)
tsu(P6D–E)
tsu(P7D–E)
tsu(P8D–E)
tsu(P10D–E)
th(E–P0D)
th(E–P1D)
th(E–P2D)
th(E–P3D)
th(E–P4D)
th(E–P5D)
th(E–P6D)
th(E–P7D)
th(E–P8D)
th(E–P10D)
Min.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits
Unit
Parameter
83
33
33
200
200
200
200
200
200
200
200
200
200
0
0
0
0
0
0
0
0
0
0
External clock input cycle time (Note 2)
External clock input high-level pulse width (Note 3)
External clock input low-level pulse width (Note 3)
External clock rise time
External clock fall time
Port P0 input setup time
Port P1 input setup time
Port P2 input setup time
Port P3 input setup time
Port P4 input setup time
Port P5 input setup time
Port P6 input setup time
Port P7 input setup time
Port P8 input setup time
Port P10 input setup time
Port P0 input hold time
Port P1 input hold time
Port P2 input hold time
Port P3 input hold time
Port P4 input hold time
Port P5 input hold time
Port P6 input hold time
Port P7 input hold time
Port P8 input hold time
Port P10 input hold time
Symbol
Max.
15
15
Notes 1: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz.
2: When the main clock division selection bit = “1,” the minimum value of tc = 166 ns.
3: When the main clock division selection bit = “1,” values of tw(H)/tc and tw(L)/tc must be set to values
from 0.45 through 0.55.
td(E–P0Q)
td(E–P1Q)
td(E–P2Q)
td(E–P3Q)
td(E–P4Q)
td(E–P5Q)
td(E–P6Q)
td(E–P7Q)
td(E–P8Q)
td(E–P9Q)
td(E–P10Q)
Port P0 data output delay time
Port P1 data output delay time
Port P2 data output delay time
Port P3 data output delay time
Port P4 data output delay time
Port P5 data output delay time
Port P6 data output delay time
Port P7 data output delay time
Port P8 data output delay time
Port P9 data output delay time
Port P10 data output delay time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Symbol
Max.
300
300
300
300
300
300
300
300
300
300
300
Min.
Limits
Parameter
Switching characteristics (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = –40 to 85 °C, f(XIN) = 12 MHz (Note), unless
otherwise noted)
Measuring conditions
Fig. 18.4.1
Note: This is applied when the main clock division selection bit = “0” and f(f2) = 6 MHz.



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