7733 datasheet(132/940 Pages) RENESAS

132 / 940 page

TIMER A

7733 Group User’s Manual

6–21

6.4 Event counter mode

Fig. 6.4.1 Structures of timer A0 and A1 mode registers and timer A0 and A1 registers in event

counter mode

Timer A0 mode register (address 5616)

Timer A1 mode register (address 5716)



00 1

Bit

Up-down switching factor

selection bit

Count polarity selection bit

Bit name

These bits are ignored in the event counter mode.

Must be fixed to “0” in the event counter mode.

Functions

0: Counts at falling edge of external signal

1: Counts at rising edge of external signal

0: Contents of the up-down flag

1: A signal which is input to pin TA0OUT or TA1OUT

At reset

Pulse output function

selection bit

Operating mode selection

bits

0: No pulse is output. (Pin TA0OUT or TA1OUT

functions as a programmable I/O port.)

1: Pulse is output. (Pin TA0OUT or TA1OUT

functions as a pulse output pin.)

0 1: Event counter mode

b1 b0

b0 b7

(b15)

(b8)

Timer A0 register (addresses 4716, 4616)

Timer A1 register (addresses 4916, 4816)

15 to 0 Values 000016 to FFFF16 can be set.

Assuming that the set value = n, counter

divides the count source frequency by (n + 1)

in down-counting, or by (FFFF16 – n + 1) in up-

counting.

At reading this register, the counter value is

read out.

Undefined

Bit

Functions

At reset



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