H83069RF datasheet(281/1003 Pages) RENESAS

281 / 1003 page

Rev. 5.0, 09/04, page 259 of 978

8.3

Port 2

8.3.1

Overview

Port 2 is an 8-bit input/output port also used for address output, with the pin configuration shown

in figure 8.2. The pin functions differ according to the operating mode.

In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 2 consists of address bus

output pins (A

15 to A8). In mode 5 (expanded mode with on-chip ROM enabled), settings in the

port 2 data direction register (P2DDR) can designate pins for address bus output (A

15 to A8) or

generic input. In mode 7 (single-chip mode), port 2 is a generic input/output port.

When DRAM is connected to areas 2 to 5, A

12 to A8 output row and column addresses in read and

write cycles. For details see section 6.5, DRAM Interface.

Port 2 has software-programmable built-in pull-up transistors.

Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or

a darlington transistor pair.

Port 2

P2 /A

P2 (input/output)

(output)

A (output)

Port 2 pins

Mode 7

Modes 1 to 4

P2 (input)/A

(output)

P2 (input)/A

(output)

P2 (input)/A

(output)

P2 (input)/A

(output)

P2 (input)/A

(output)

P2 (input)/A

(output)

P2 (input)/A

(output)

P2 (input)/A

(output)

Mode 5

Figure 8.2 Port 2 Pin Configuration

H83069RF Datasheet(PDF) 281 Page - Renesas Technology Corp

H83069RF Datasheet(HTML) 281 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL