TMP421 datasheet(16/30 Pages) TI

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SOFTWARE RESET

BUS OVERVIEW

GENERAL CALL RESET

SERIAL INTERFACE

IDENTIFICATION REGISTERS

TMP421

TMP422

TMP423

SBOS398B – JULY 2007 – REVISED MARCH 2008

address FEh. The device ID is obtained by reading

from pointer address FFh. The TMP421/22/23 each

The TMP421/22/23 may be reset by writing any value

return 55h for the manufacturer code. The TMP421

to the Software Reset Register (pointer address

returns 21h for the device ID; the TMP422 returns

FCh). This action restores the power-on reset state to

22h for the device ID; and the TMP423 returns 23h

all of the TMP421/22/23 registers as well as aborts

for the device ID. These registers are read-only.

any conversion in process. The TMP421/22/23 also

support reset via the two-wire general call address

(0000 0000). The General Call Reset section contains

more information.

The TMP421/22/23 are SMBus interface-compatible.

In SMBus protocol, the device that initiates the

Table 8. n-Factor Range

transfer is called a master, and the devices controlled

by the master are slaves. The bus must be controlled

NADJUST

by a master device that generates the serial clock

BINARY

HEX

DECIMAL

(SCL), controls the bus access, and generates the

0111 1111

127

1.747977

START and STOP conditions.

0000 1010

1.042759

To address a specific device, a START condition is

0000 1000

1.035616

initiated. START is indicated by pulling the data line

0000 0110

1.028571

(SDA) from a high-to-low logic level while SCL is

0000 0100

1.021622

high. All slaves on the bus shift in the slave address

0000 0010

1.014765

byte, with the last bit indicating whether a read or

0000 0001

1.011371

write operation is intended. During the ninth clock

0000 0000

1.008

pulse, the slave being addressed responds to the

1111 1111

–1

1.004651

master by generating an Acknowledge and pulling

1111 1110

–2

1.001325

SDA low.

1111 1100

–4

0.994737

Data transfer is then initiated and sent over eight

1111 1010

–6

0.988235

clock pulses followed by an Acknowledge bit. During

1111 1000

–8

0.981818

data transfer SDA must remain stable while SCL is

1111 0110

–10

0.975484

high, because any change in SDA while SCL is high

1000 0000

–128

0.706542

is interpreted as a control signal.

Once all data have been transferred, the master

generates a STOP condition. STOP is indicated by

pulling SDA from low to high, while SCL is high.

The TMP421/22/23 support reset via the two-wire

General

Call

address

00h

(0000

0000b).

The

TMP421/22/23

acknowledge

the

General

Call

address and respond to the second byte. If the

The TMP421/22/23 operate only as a slave device on

second byte is 06h (0000 0110b), the TMP421/22/23

either the two-wire bus or the SMBus. Connections to

execute a software reset. This software reset restores

either bus are made via the open-drain I/O lines, SDA

the

power-on

reset

state

all

TMP421/22/23

and SCL. The SDA and SCL pins feature integrated

registers, and aborts any conversion in progress. The

spike suppression filters and Schmitt triggers to

TMP421/22/23 take no action in response to other

minimize the effects of input spikes and bus noise.

values in the second byte.

The TMP421/22/23 support the transmission protocol

for fast (1kHz to 400kHz) and high-speed (1kHz to

3.4MHz) modes. All data bytes are transmitted MSB

first.

The TMP421/22/23 allow for the

two-wire

bus

controller to query the device for manufacturer and

device IDs to enable software identification of the

device at the particular two-wire bus address. The

manufacturer ID is obtained by reading from pointer

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