www.ti.com

TIMING DIAGRAMS

SCL

SDA

t

(LOW)

t

R

t

F

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(BUF)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

P

S

S

P

TMP421

TMP422

TMP423

SBOS398B – JULY 2007 – REVISED MARCH 2008

Data Transfer: The number of data bytes transferred

between a START and a STOP condition is not

The

TMP421/22/23

are

two-wire

and

limited and is determined by the master device. The

SMBus-compatible. Figure 16 to Figure 19 describe

receiver acknowledges data transfer.

the

timing

for

various

operations

on

the

TMP421/22/23. Parameters for Figure 16 are defined

Acknowledge:

Each

receiving

device,

when

in Table 11. Bus definitions are:

addressed, is obliged to generate an Acknowledge

bit. A device that acknowledges must pull down the

Bus Idle: Both SDA and SCL lines remain high.

SDA line during the Acknowledge clock pulse in such

a way that the SDA line is stable low during the high

Start Data Transfer: A change in the state of the

period of the Acknowledge clock pulse. Setup and

SDA line, from high to low, while the SCL line is high,

hold times must be taken into account. On a master

defines a START condition. Each data transfer

receive, data transfer termination can be signaled by

initiates with a START condition. Denoted as S in

the master generating a Not-Acknowledge on the last

Figure 16.

byte that has been transmitted by the slave.

Stop Data Transfer: A change in the state of the

SDA line from low to high while the SCL line is high

defines

a

STOP

condition.

Each

data

transfer

terminates

with

a

repeated

START

or

STOP

condition. Denoted as P in Figure 16.

Figure 16. Two-Wire Timing Diagram

Table 11. Timing Characteristics for Figure 16

FAST MODE

HIGH-SPEED MODE

PARAMETER

MIN

MAX

MIN

MAX

UNIT

SCL Operating Frequency

0.001

0.4

0.001

3.4

MHz

Bus Free Time Between STOP and START Condition

600

160

ns

Hold time after repeated START condition. After this period, the first clock

100

100

ns

is generated.

Repeated START Condition Setup Time

100

100

ns

STOP Condition Setup Time

100

100

ns

Data Hold Time

ns

Data Setup Time

100

10

ns

SCL Clock LOW Period

1300

160

ns

SCL Clock HIGH Period

600

60

ns

Clock/Data Fall Time

300

160

ns

Clock/Data Rise Time

300

160

ns

for SCL

≤ 100kHz

1000

(1)

For cases with fall time of SCL less than 20ns and/or the rise or fall time of SDA less than 20ns, the hold time should be greater than

20ns.

(2)

For cases with a fall time of SCL less than 10ns and/or the rise or fall time of SDA less than 10ns, the hold time should be greater than

10ns.

Copyright © 2007–2008, Texas Instruments Incorporated

Submit Documentation Feedback

19

Product Folder Link(s): TMP421 TMP422 TMP423