Dual 24-bit 40 MIPS DSP Cores

8 bit Microcontroller

4 receive and 5 transmit stereo channels of

Serial Audio Interface

Synchronous Serial Interface for communica-

tion with external processor

FIFO based mailboxes for inter-processor

communications

External Memory Interface to 128Kb SRAM or

1Mb DRAM

CORDIC co-processor

Programmable PLL to suite wide range of ex-

ternal crystal oscillation frequencies

SPI control interface

Powerful debug interfaces

1280 words Program Memory for DSP1, 768

words Program Memory for DSP0

256 words X and Y Data RAM and Data ROM

for each DSP

256 byte Data RAM for Microcontroller

768 byte Auxiliary RAM for Microcontroller

DESCRIPTION

The device is a high-performance Digital Signal

Processing IC particularly suited to Audio applica-

tions. The device contains two 24-bit 40 MIPS

DSP cores delivering a total of 80 MIPS of DSP

processing power. There is also an embedded 8-

bit Microcontroller to handle all control functions.

All data and program memories for both DSP

cores are on-chip. A variety of highly programma-

ble and flexible peripheral blocks for both the Mi-

crocontroller and the DSPs have been integrated

to form a powerful audio processing system on a

single chip.

This is preliminary information on a new product now in development. Details are subject to change without notice.

July 1999

®

Host

Interface 0

DEBUG

Interface

DSP0

CORE

M8051

CORE

Mi cro

Memory

Interface

AUX-RAM

768 Bytes

C ordic

Ari thmetic

U nit

DSP1

CORE

Host

Interface 1

Serial

Audio

Interface

Synchronous

Audio

Interface

SRAM/

D RAM

Interface

XCHG

Interface

XDB0

XAB0

XDB1

XAB1

X-RAM0

X-ROM0

Y-RAM0

Y-ROM0

P-RAM0

P-ROM0

P-RAM1

P-ROM1

Y-RAM1

Y-ROM1

X-RAM1

X-ROM1

AUX-RAM

256 Bytes

Watchdog

Timer

PLL

Clock

Oscillator

DCLK

BLOCK DIAGRAM

TQFP100

TDA7503

DUAL DSP PLUS MICRO FOR AUDIO APPLICATIONS

PRODUCT PREVIEW

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