TDA7503 datasheet(4/26 Pages) STMICROELECTRONICS

4 / 26 page

Name

Type

Reset

Status (1)

Function

SRA_D5/DRA1

I/O

O, High

DSP SRAM Multiplexed Address/Data Line 5/DSP DRAM Address Line

1. When in SRAM Mode these pins act as the EMI multiplexed address

and data line 5. When in DRAM Mode they act as the EMI address line 1.

SRA_D6/DRA2

I/O

O, High

DSP SRAM Multiplexed Address/Data Line 6/DSP DRAM Address Line

2. When in SRAM Mode these pins act as the EMI multiplexed address

and data line 6. When in DRAM Mode they act as the EMI address line 2.

SRA_D7/DRA3

I/O

O, High

DSP SRAM Multiplexed Address/Data Line 7/DSP DRAM Address Line

3. When in SRAM Mode these pins act as the EMI multiplexed address

and data line 7. When in DRAM Mode they act as the EMI address line 3.

SRA8/DRA4

High

DSP SRAM Address Line 8/DSP DRAM Address Line 4. When in SRAM

Mode these pins act as the EMI address line 8. When in DRAM Mode

they act as the EMI address line 4.

SRA9/DRA5

High

DSP SRAM Address Line 9/DSP DRAM Address Line 5. When in SRAM

Mode these pins act as the EMI address line 9. When in DRAM Mode

they act as the EMI address line 5.

SRA10/DRA6

High

DSP SRAM Address Line 10/DSP DRAM Address Line 6. When in

SRAM Mode these pins act as the EMI address line 10.When in DRAM

Mode they act as the EMI address line 6.

SRA11/DRA7

High

DSP SRAM Address Line 11/DSP DRAM Address Line 7. When in

SRAM Mode these pins act as the EMI address line 11. When in DRAM

Mode they act as the EMI address line 7.

SRA12/DRA8

High

DSP SRAM Address Line 12/DSP DRAM Address Line 8. When in

SRAM Mode these pins act as the EMI address line 12. When in DRAM

Mode they act as the EMI address line 8.

SRA13/RAS

High

DSP SRAM Address Line 13/DRAM Row Address Strobe. When in

SRAM Mode this pin acts as the EMI address lines 13. When in DRAM

Mode this pin acts as the row address strobe.

ALE/CAS

High

DSP SRAM Address latch enable/colomn Address. When in SRAM

Mode this pin acts as the EMI Address Latch Enable. When in DRAM

Mode this pin acts as the column address strobe.

DWR

High

DSP SRAM Write Enable/DRAM Write Enable. This pin serves as the

write enable for the EMI when in DRAM and SRAM Modes.

DRD

High

DSP SRAM Read Enable/DRAM Read Enable. This pin serves as the

read enable for the EMI when in DRAM and SRAM Modes.

DBCK/OS1

I/O

Debug Port Bit Clock/Chip Status 1. The serial clock for the Debug Port

is provided when an input. When an output, together with OS0 provides

information about the chip status. Can also be used as GPIO for the

8051.

DBIN/OS0

I/O

Debug Port Serial Input/Chip Status 0. The serial data input for the

Debug Port is provided when an input. When an output, together with

OS1 provides information about the chip status. Can also be used as

GPIO for the 8051.

DBOUT

I/O

Debug Port Serial Output. The serial data output for the Debug Port. Can

also be used as a GPIO for the 8051.

DBRQN

–

Debug Port Request Input. Means of entering the Debug mode of

operation.

DBSEL

–

Debug Port MUX Selection. Selects either DSP0 or DSP1 to be

connected to the Debug Port pins.

RA8(P2.0)

I/O

Microcontroller High Byte Address Lines. This pin is the address line 8 of

a 16 bit address, for external EPROM and memory mapped devices. It

can also act as GPIO using the P2 and P2DIR registers.

RA9(P2.1)

I/O

Microcontroller High Byte Address Lines. This pin is the address line 9 of

a 16 bit address, for external EPROM and memory mapped devices. It

can also act as GPIO using the P2 and P2DIR registers.

PIN DESCRIPTION (continued)

TDA7503

4/26

TDA7503 Datasheet(PDF) 4 Page - STMicroelectronics

TDA7503 Datasheet(HTML) 4 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datasheet Download

Link URL