TDA7503 datasheet(3/26 Pages) STMICROELECTRONICS

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PIN DESCRIPTION

Name

Type

Reset

Status (1)

Function

LRCKR

–

Audio Serial Port Receive Left/Right Frame Sync. The Left/Right select

signal for received serial audio data. This signal has a frequency equal to

the audio sample rate.

SCLKR

–

Audio Serial Port Receive Bit Clock. SCLK clocks received digital audio

data into pins SDI0, SDI1, SDI2, and SDI3

SDI0

–

Stereo Digital Audio Data. SDI0 is a stereo digital audio data input pin

channel 0.

SDI1

–

Stereo Digital Audio Data. SDI1 is a stereo digital audio data input pin

channel 1.

SDI2

–

Stereo Digital Audio Data. SDI2 is a stereo digital audio data input pin

channel 2.

SDI3

–

Stereo Digital Audio Data / Serial Receive Data. SDI3 is a stereo digital

audio data input pin and is multiplexed with the SSI’s Serial Receive

Data Input channel 3.

LRCKT

–

Audio Serial Port Transmit Left/Right Frame Sync /Frame Sync. The

Left/Right select signal for transmitted serial audio data. This signal has a

frequency equal to the audio sample rate. This signal is multiplexed with

the SSI’s Frame Sync Input.

SCLKT

–

Audio Serial Port Transmit Bit Clock/SSI Serial Bit Clock. SCLK clocks

digital audio data out of pins SDO0, SDO1, SD02, SD03, and SD04. This

pin is multiplexed with the SSI’s serial bit clock.

SDO0

High

Stereo Digital Audio Data. SDO0 is a stereo digital audio data output pin

channel 0.

SDO1

High

Stereo Digital Audio Data. SDO1 is a stereo digital audio data output pin

channel 1.

SDO2

High

Stereo Digital Audio Data. SDO2 is a stereo digital audio data output pin

channel 2.

SDO3

High

Stereo Digital Audio Data. SDO3 is a stereo digital audio data output pin

channel 3.

SDO4

High

Stereo Digital Audio Data /Serial Transmit Data. SDO4 is a stereo digital

audio data output pin and is multiplexed with the SSI’s Serial Transmit

Data Output channel 4.

SCANEN

–

SCAN Enable. Enable SCAN Path and MUXing of SCANIN and SCANOUT

Pins.

TESTEN

–

Test Enable. Enable Scan Mode Clocks. An active low signal will enable

the same clock to all scan chains. This pin also makes all latches

transparent.

SRA_D0/DRD0

I/O

DSP SRAM Multiplexed Address/Data Line 0/DSP DRAM Data Line

0.When in SRAM Mode these pins act as the EMI multiplexed address

and data line 0. When in DRAM Mode they act as the EMI data line 0.

SRA_D1/DRD1

I/O

DSP SRAM Multiplexed Address/Data Line 1/DSP DRAM Data Line

1.When in SRAM Mode these pins act as the EMI multiplexed address

and data line 1. When in DRAM Mode they act as the EMI data line 1.

SRA_D2/DRD2

I/O

DSP SRAM Multiplexed Address/Data Line 2/DSP DRAM Data Line

2.When in SRAM Mode these pins act as the EMI multiplexed address

and data line 2. When in DRAM Mode they act as the EMI data line 2.

SRA_D3/DRD3

I/O

DSP SRAM Multiplexed Address/Data Line 3/DSP DRAM Data Line

3.When in SRAM Mode these pins act as the EMI multiplexed address

and data line 3. When in DRAM Mode they act as the EMI data line 3.

SRA_D4/DRA0

I/O

O, High

DSP SRAM Multiplexed Address/Data Line 4/DSP DRAM Address Line

0. When in SRAM Mode these pins act as the EMI multiplexed address

and data line 4. When in DRAM Mode they act as the EMI address line 0.

TDA7503

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