TDA7503 datasheet(22/26 Pages) STMICROELECTRONICS

22 / 26 page

DSP1

$0000

X-Space

P-Space

$FFFF

X-RAM

P-RAM

X-ROM

Not Accessible Not Accessible

Y-Space

Y-RAM

Y-ROM

Not Accessible

Boot-Space

Not Accessible

Boot-ROM

$04FF

$0500

$003F

$00FF

$FFC0

$0040

$01FF

$0200

$0100

$FFBF

DSP0

$0000

X-Space

P-Space

$FFFF

X-RAM

P-RAM

X-ROM

Not Accessible Not Accessible

X-Peripherals

Y-Space

Y-RAM

Y-ROM

Not Accessible

Boot-Space

Not Accessible

Boot-ROM

$003F

$00FF

$FFC0

$0040

$02FF

$0300

$0100

$FFBF

$01FF

$0200

X-Peripherals

Figure 20. DSP1 and DSP0 Memory Spaces.

Transmit and Receive Interrupt Logic triggers

on Left/Right data pairs

Receive and Transmit Data Registers have

two locations to hold left and right data.

Synchronous Serial Interface (SSI)

The SSI is used for communication with devices

with a conventional serial interface (not I2S ste-

reo serial audio interface). The SSI shares some

pins with the SAI. When the SSI is activated,

some of the SAI pins are switched from the SAI

to the SSI. The SAI and SSI can operate in paral-

lel.

The features of the SSI are listed below.

Slave operating mode, FSYNC and SSISCK

are inputs.

Data sizes of 8, 16, and 24 bits are supported.

Frame Sync (FSYNC) and SCK (SSISCK) sig-

nals connected to both the receiver and trans-

mitter.

Normal mode or Network mode possible.

XCHG Interface (DSP to DSP Exchange Inter-

face)

The Exchange Interface peripheral provides bidi-

rectional communication between DSP0 and

DSP1. Both 24 bit word data and four bit Flag

data can be exchanged. A FIFO is utilized for re-

ceived data. It minimizes the number of times an

Exchange Interrupt Service Routine would have

to be called if multi-word blocks of data were to

be received. The Transmit FIFO is in effect the

Receive FIFO of the other DSP and is written di-

rectly by the transmitting DSP. The features of

the XCHG are listed below.

10 Word XCHG Receive FIFO on both DSPs

Four Flags for each XCHG for DSP to DSP

signaling

Condition flags can optionally trigger interrupts

on both DSPs

Host Interface(HI)

The DSPs communicate with the 8051 through

the Host Interface. There is a separate HI for

each of the DSPs. Two Host Interfaces are in-

cluded. HI0 for Host to DSP0 communication,

and HI1 for Host to DSP1 communication. The

TDA7503

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