TDA7503 datasheet(23/26 Pages) STMICROELECTRONICS

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features of the HI are listed below.

8 Word Host Receive FIFO - DSP Side

4 Word Host Receive FIFO - Host (8051) Side

Two Flags for each HI for DSP to Host signal-

ing (can optionally trigger interrupts)

Command Vector Register allows Host to trig-

ger any DSP vectored interrupt

DRAM/SRAM Interface (EMI)

The External DRAM/SRAM Interface is viewed as

a memory mapped peripheral. Data transfers are

performed by moving data into/from data regis-

ters and the control is exercised by polling status

flags in the control/status register or by servicing

interrupts. An external memory write is executed

by writing data into the EMI Data Write Register.

An external memory read operation is executed

by either writing to the offset register or reading

the EMI Data Read Register, depending on the

configuration.

The features of the EMI are listed below.

Data bus width fixed at 4 bits for DRAM and 8

bits for SRAM.

Data word length choices of 16 or 24 bits.

Nine DRAM address lines means 218 = 256KB

addressable DRAM.

Refresh rate for DRAM can be chosen among

eight divider factor.

SRAM relative addressing mode with multi-

plexed address/data lines; 214= 16KB ad-

dressable SRAM.

Four SRAM Timing choices.

Two Read Offset Registers.

Debug Interface

The Debug Port is multiplexed to both of the DSP

Cores via a select pin. Only one DSP can be de-

bugged at a time. The debug logic is contained in

the core design of the DSP. The features of the

Debug Port are listed below:

Breakpoint Logic

Trace Logic

Single stepping

Instruction Injection

Program Disassembly

CORDIC Co-Processor

The CORDIC Co-Processor is used to convert

rectangular to polar coordinates. .

The CORDIC Unit has an 18 Bit data path

throughout. When reading 24 bit words from the

DSP the upper 6 bits are truncated. When writing

to the DSP the upper 6 bits are zeroed.

Either DSP may write an X and Y coordinate to

the CORDIC unit and, 17 clock cycles later, the

magnitude and angle information will be available

from the CORDIC Unit.

8051 Embedded Microcontroller

The microcontroller serves as the on-chip system

controller and operates from 64K of external

EPROM with 1K of internal RAM. In addition, it

contains a small program in internal RAM that al-

lows the micro to program the external EPROM.

The micro will boot a network interface program

from external EPROM. If a command to program

the EPROM is received from the network then the

following sequence will be initiated: The micro will

read a ROM image from the network via a net-

work chip attached to the micro’s SPI. Then the

micro will switch to running out of internal RAM

and begin programming the external EPROM

with the image read from the network. This allows

the personality of the system to be set after the

system has been manufactured. The external

EPROM also holds the DSP programs and initial-

izing values. The micro will copy these images to

the DSP via an on-chip host interface (HI).

In addition to the 8051 Core the following mem-

ory and control functions are required:

Internal Memory Interface to 256 Bytes of Sin-

gle Port Static RAM and 768 Bytes of AUX-

RAM

External Memory Interface to EPROM and

Memory Mapped Peripheral I/O

Host Interface for Micro to DSP Communica-

tion

Serial Peripheral Interface (SPI)

Control Interface for Interrupts and GPIO

PLL Clock Oscillator

Internal Memory Interface

The 8051 requires an internal memory interface

to connect to the internal 256 RAM locations and

the 768 Auxiliary RAM.

Micro Memory Interface

The 8051 core requires an external memory inter-

face to connect to external program memory and

memory mapped peripherals. This is imple-

mented like the standard 80C51 Port 2/Port 0

Multiplexed 16 Bit Address/8 Bit Data Bus. . The

signals RD, WR, XPSEN, and XALE will also be

output. The External Memory Interface must also

have circuitry to program the external EPROM (or

any non-volatile memory) in-circuit. This means

that the normal operation of the external memory

interface must be altered to handle the program

timing of the EPROM. By treating the Port 2/Port

0 pins as GPIO the programming can be

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