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AD5100

Rev. 0 | Page 16 of 36

V4MON

V4MON is a low voltage monitoring input that controls the RESET

function of an external device or provides a comparator output,

V4OUT. The V4MON pin is monitored by a comparator to detect an

undervoltage condition. It is designed with 5% hysteresis.

When the V4MON input drops below the programmed UV thresh-

old, the comparator becomes active immediately, indicating that

a UV condition has occurred. Due to hysteresis, the V4MON input

must be brought above the programmed UV threshold by 5%

before the comparator becomes inactive, indicating that the UV

condition has gone away (see Figure 11).

V4MON

V4MON_UV

COMPARATOR

INACTIVE

COMPARATOR

INACTIVE

HYSTERESIS

Figure 11. V4MON Hysteresis

The V4MON comparator is used to control the V4OUT pin and (in

conjunction with a hold timer) to control the RESET pin. To

configure V4MON to control the RESET pin, set Register 0x0D[3]

to 0. Setting this bit to 1 prevents V4MON from causing RESET to

activate.

V4MON input voltage range is up to 30 V. It has an 8-step

programmable reset threshold (Register 0x06) from 1.67 V to

7.96 V, with an 8-step 0.1 ms to 200 ms reset hold time

(tRS_HOLD).

The V4MON, RESET, and V4OUT timing diagrams are shown in

. The range of thresholds is shown in

, and the

programming code for the selected threshold is found in

The default monitoring threshold is 7.54 V. Similarly, the range

of reset hold time is shown in

, and the programming

code of the selected timing is found in

Figure 12

Table 6

Table 8

Table 9

V4MON exhibits typical input resistance of 665 kΩ that users

should take into account for loading effect.

WATCHDOG INPUT

The watchdog input (WDI) circuit attempts to reset the system

to a known good state if a software or hardware glitch renders

the system processor inactive for a duration that is longer than

the timeout period. The timeout period, tWD, is programmable

in eight steps from 100 ms to 2000 ms. The watchdog circuit is

independent of any CPU clock that the watchdog is monitoring.

The range of watchdog timeout is shown in Table 8, and the

programming code of the selected timeout is found in Table 9.

The default timeout is 1500 ms.

The watchdog is disabled during power-up. WDI starts monitor-

ing once RESET is high. The AD5100 provides a standard or

advanced watchdog monitoring function. Register 0x0F[3] sets

the watchdog function to either standard or advanced mode.

•

V4MON

V4OUT

tGLITCH

RESET

NOTES

1. * = PROGRAMMABLE.

2. MOST APPLICATIONS USING V4OUT REQUIRE DISABLING OF V4MON TRIGGERED RESET.

tRS_HOLD*

tRS_DELAY

Figure 12. V4MON , RESET, and V4OUT Timing Diagrams

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