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AD5100

Rev. 0 | Page 19 of 36

OUTPUTS

SHUTDOWN OUTPUT, SHDN

The shutdown output, SHDN, is triggered by V1MON or V2MON

over- or underthreshold values, or as the result of a failed

watchdog input. SHDN can also be asserted low at any time by

writing to certain registers on the AD5100.

The shutdown generator asserts a logic low SHDN signal based

on the following conditions:

•

During power-up

•

When V1MON goes over or under the threshold (see Figure 7)

•

When V2MON is below the turn-on threshold during the

rising edge or the turn-off threshold during the falling edge

in level-sensitive mode (see Figure 7)

•

When the external monitoring processor cannot issue

the necessary WDI signal and advanced WDI mode is

selected (see Figure 10 and Figure 9)

•

I2C® programmed shutdown

To activate SHDN by writing to the part, the user must first

enable this feature by writing to Register 0x18[4].

•

Once the feature is enabled, control of SHDN is achieved by

writing to Register 0x16[2].

•

software

•

The SHDN signal is released after the programmable hold time,

tSD_HOLD. The SHDN output is push-pull configured with an I2C-

selectable rail voltage of either V1MON in default or internal VREG.

•

Figure 16 shows the SHDN output configuration. Pull-down

Resistor R1 ensures that SHDN is pulled to ground when the

AD5100 is not powered. When AD5100 is powered, M2a and

M2b are both on. M2a has relatively lower impedance than M2b

and R1 so the SHDN remains low at shutdown. When the

AD5100 settles, SW1 is turned on. M1 is stronger than M2a so

SHDN is pulled to the rail, which takes AD5100 out of the

shutdown mode.

In some applications, the AD5100 may monitor and control

power regulators where the input and enable pins are next to

each other in a fine pitch. This may pose reliability concerns

under some abnormal conditions. To prevent errors from happen-

ing, the AD5100 shutdown output features smart-load detection

to ensure that the shutdown responds. For example, if the car

battery has not started for a long time, a resistive dendrite may

have formed across the SHDN pin and the battery terminal

(V1MON). The dendrite is blown immediately because M2a is

designed with adequate current sinking capability and remains in

the on position to offer such protection. In another situation, if

the SHDN pin is hard-shorted to the 12 V battery, the short-

circuit detector opens SW2 and limits the current by the high

impedance M2b.

V1MON

M2A

M2B

SW3

SW1

SW2

LOW-Z

HIGH-Z

SHDN

# *

VREG

LEVEL

SHIFTER

SHORT-CIRCUIT

DETECT

NOTES

1. # = I2C SELECTABLE

2. * = DEFAULT

Figure 16. Shutdown Output

RESET OUTPUT, RESET

The reset output, RESET, is triggered by V3MON or V4MON

underthreshold values. RESET activation can also be the result

of the processor not generating the proper watchdog signal, if

MR input is triggered, or if SHDN is activated.

The reset generator asserts the RESET signal based on the

following conditions:

•

During power-up

•

When V3MON drops below the threshold (see Figure 10)

•

When V4MON drops below the threshold (see Figure 12)

•

When SHDN output is asserted (see

and

);

Figure 7

Figure 14

RESET follows SHDN hold and delay timings if triggered by

the SHDN output

•

When the external monitoring processor cannot issue the

necessary WDI signal (see Figure 13 and Figure 14)

•

When MR is asserted (see

)

Figure 15

RESET is active low by default, but can be configured for active

high operation. Register 0x0D[1] controls the activation

polarity of RESET.

•

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