OPA4872MDREP datasheet(16/24 Pages) TI

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DRIVING CAPACITIVE LOADS

I )

OSO_envelope

I xR

±½- -

½ ´

(V )

PSRR

± ½ -

(V )

S+ ½ ´

PSRR+

(7)

±½- - - ½ ´

( 6)

±½ - ½ ´

= 29.2mV

+523

18 A

W ´ ± m

´ ±

10mV+75

14 A

(8)

DISTORTION PERFORMANCE

DC ACCURACY

OPA4872-EP

SBOS444 – DECEMBER 2008........................................................................................................................................................................................... www.ti.com

One of the most demanding, yet very common load

conditions, is capacitive loading. Often, the capacitive

load is the input of an analog-to-digital converter

(ADC)—including additional external capacitance that

Where:

may be recommended to improve ADC linearity. A

RS: Input resistance seen by R0, R1, G0, G1, B0,

high-speed device such as the OPA4872 can be very

or B1.

susceptible to decreased stability and closed-loop

response peaking when a capacitive load is placed

Ib: Noninverting input bias current

directly on the output pin. When the device open-loop

Ibi: Inverting input bias current

output resistance is considered, this capacitive load

G: Gain

introduces an additional pole in the signal path that

VS+: Positive supply voltage

can decrease the phase margin. Several external

solutions to this problem have been suggested. When

VS–: Negative supply voltage

the primary considerations are frequency response

PSRR+: Positive supply PSRR

flatness, pulse response fidelity, and/or distortion, the

PSRR–: Negative supply PSRR

simplest and most effective solution is to isolate the

VOS: Input Offset Voltage

capacitive load from the feedback loop by inserting a

series isolation resistor between the amplifier output

Evaluating

the

front-page

schematic,

using

and the capacitive load. This isolation resistor does

worst-case, +25°C offset voltage, bias current and

not eliminate the pole from the loop response, but

PSRR specifications and operating at ±6 V, gives a

rather shifts it and adds a zero at a higher frequency.

worst-case output equal to Equation 8:

The additional zero acts to cancel the phase lag from

the capacitive load pole, thus increasing the phase

margin and improving stability.

The Typical Characteristics show the recommended

RS versus capacitive load and the resulting frequency

response at the load; see Figure 5. Parasitic

capacitive loads greater than 2 pF can begin to

degrade the performance of the OPA4872. Long PCB

The OPA4872 provides good distortion performance

traces,

unmatched

cables,

and

connections

into a 150-

Ω load on ±5-V supplies. Relative to

multiple devices can easily cause this value to be

alternative

solutions,

provides

exceptional

exceeded. Always consider this effect carefully, and

performance into lighter loads. Generally, until the

add the recommended series resistor as close as

fundamental signal reaches very high frequency or

possible to the OPA4872 output pin (see the Board

power levels, the 2nd harmonic dominates the

Layout Guidelines section).

distortion with a negligible 3rd harmonic component.

Focusing then on the 2nd harmonic, increasing the

load impedance directly improves distortion. Also,

The OPA4872 offers excellent dc signal accuracy.

providing an additional supply decoupling capacitor

Parameters that influence the output dc offset voltage

(0.01

µF) between the supply pins (for bipolar

are:

operation) improves the 2nd-order distortion slightly

• Output offset voltage

(3 dB to 6 dB).

• Input bias current

In most op amps, increasing the output voltage swing

• Gain error

increases harmonic distortion directly. The Typical

• Power-supply rejection ratio

Characteristics show the 2nd harmonic increasing at

a little less than the expected 2X rate while the 3rd

• Temperature

harmonic increases at a little less than the expected

3X rate. Where the test power doubles, the 2nd

Leaving both temperature and gain error parameters

harmonic increases only by less than the expected 6

aside, the output offset voltage envelope can be

dB, whereas the 3rd harmonic increases by less than

described as shown in Equation 7:

the expected 12 dB.

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