OPA4872MDREP datasheet(19/24 Pages) TI

19 / 24 page

P =10V

11.7mA+ 5 /[4

(150

||1046 )] =165mW

(

)

MaximumT =+85 C+(165mW

80 C/W)=98 C

BOARD LAYOUT GUIDELINES

OPA4872-EP

www.ti.com........................................................................................................................................................................................... SBOS444 – DECEMBER 2008

As a worst-case example, compute the maximum TJ

Again, keep their leads and PCB trace length as short

using an OPA4872ID in the circuit of Figure 27

as possible. Never use wirewound type resistors in a

operating

the

maximum

specified

ambient

high-frequency

application.

Other

network

temperature of +85°C with its output driving a

components, such as noninverting input termination

grounded 100-

Ω load to +2.5 V:

resistors, should also be placed close to the package.

d) Connections to other wideband devices on the

board may be made with short direct traces or

through onboard transmission lines. For short

connections, consider the trace and the input to the

next device as a lumped capacitive load. Relatively

This worst-case condition does not exceed the

wide traces (50mils to 100mils) should be used,

maximum

junction

temperature.

Normally,

this

preferably with ground and power planes opened up

extreme case is not encountered.

around them.

Estimate the total capacitive load and set RS from the

plot of Figure 5. Low parasitic capacitive loads

Achieving

optimum

performance

with

(greater than 5 pF) may not need an RS because the

high-frequency

amplifier

such

the

OPA4872

OPA4872 is nominally compensated to operate with a

requires careful attention to board layout parasitics

2-pF parasitic load. If a long trace is required, and the

and external component types. Recommendations to

6dB signal loss intrinsic to a doubly-terminated

optimize performance include:

transmission line is acceptable, implement a matched

a) Minimize parasitic capacitance to any ac

impedance transmission line using microstrip or

ground for all of the signal I/O pins. Parasitic

stripline techniques (consult an ECL design handbook

capacitance on the output pin can cause instability;

for microstrip and stripline layout techniques). A 50-

Ω

on the noninverting input, it can react with the source

environment is normally not necessary on the board,

impedance to cause unintentional bandlimiting. To

and

fact,

higher

impedance

environment

reduce unwanted capacitance, a window around the

improves distortion as shown in the Distortion versus

signal I/O pins should be opened in all of the ground

Load plot; see Figure 7. With a characteristic board

and power planes around those pins. Otherwise,

trace impedance defined based on board material

ground and power planes should be unbroken

and trace dimensions, a matching series resistor into

elsewhere on the board.

the trace from the output of the OPA4872 is used as

well as a terminating shunt resistor at the input of the

b) Minimize the distance (< 0.25") from the

destination

device.

Remember

also

that

the

power-supply

pins

high

frequency

0.1-

µF

terminating impedance is the parallel combination of

decoupling capacitors. At the device pins, the

the shunt resistor and the input impedance of the

ground and power plane layout should not be in close

destination device; this total effective impedance

proximity to the signal I/O pins. Avoid narrow power

should be set to match the trace impedance. The

and ground traces to minimize inductance between

high output voltage and current capability of the

the

pins

and

the

decoupling

capacitors.

The

OPA4872 allow multiple destination devices to be

power-supply connections (on pins 9, 11, 13, and 15)

handled as separate transmission lines, each with its

should always be decoupled with these capacitors.

own series and shunt terminations. If the 6-dB

An optional supply decoupling capacitor across the

attenuation of a doubly-terminated transmission line

two power supplies (for bipolar operation) improves

unacceptable,

long

trace

can

2nd harmonic distortion performance. Larger (2.2

µF

series-terminated at the source end only. Treat the

to 6.8

µF) decoupling capacitors, effective at lower

trace as a capacitive load in this case and set the

frequency, should also be used on the main supply

series resistor value as shown in Figure 5. This

pins. These capacitors may be placed somewhat

configuration does not preserve signal integrity as

farther from the device and may be shared among

well

doubly-terminated

line.

the

input

several devices in the same area of the PCB.

impedance of the destination device is low, there will

c) Careful selection and placement of external

be some signal attenuation because of the voltage

components

preserves

the

high-frequency

divider

formed

the

series

output

into

the

performance of the OPA4872. Resistors should be

terminating impedance.

a very low reactance type. Surface-mount resistors

work best and allow a tighter overall layout. Metal-film

and carbon composition, axially-leaded resistors can

also

provide

good

high-frequency

performance.

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