ATF2500C datasheet(2/24 Pages) ATMEL

2 / 24 page

0777K–PLD–1/24/08

ATF2500C

The ATF2500C is organized around a single universal array. All pins and feedback terms are

always available to every macrocell. Each of the 38 logic pins are array inputs, as are the out-

puts of each flip-flop.

In the ATF2500C, four product terms are input to each sum term. Furthermore, each macrocell’s

three sum terms can be combined to provide up to 12 product terms per sum term with no per-

formance penalty. Each flip-flop is individually selectable to be either D- or T-type, providing

further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal combina-

torial feedback to the logic array.

Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-flops

may also be individually configured to have direct input pin clocking. Each output has its own

enable product term. Eight synchronous preset product terms serve local groups of either four or

eight flip-flops. Register preload functions are provided to simplify testing. All registers automati-

cally reset upon power-up.

Pin Configurations

Table 2-1.

Pin Configurations

Pin Name

Function

Logic Inputs

CLK/IN

Pin Clock and Input

I/O

Bi-directional Buffers

I/O 0,2,4...

Even I/O Buffers

I/O 1,3,5...

Odd I/O Buffers

GND

Ground

VCC

+5V Supply

Figure 2-1.

DIP

Figure 2-2.

PLCC

Note:

(PLCC package) pin 4 and pin 26 GND connections are

not required, but are recommended for improved noise

immunity.

CLK/IN

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

VCC

I/O17

I/O16

I/O15

I/O14

I/O13

I/O12

I/O6

I/O7

I/O8

I/O9

I/O10

I/O11

GND

I/O23

I/O22

I/O21

I/O20

I/O19

I/O18