5

4928H–GPS–06/08

ATR0635

2.7

Analog-to-digital Converter

The analog-to-digital converter stage has a total resolution of 1.5 bits. It comprises balanced

comparators and a sub-sampling unit, clocked by the reference frequency (f

quency spectrum of the digital output signal (f

SIGH1, is 4.348 MHz.

2.8

Baseband

The GPS baseband core includes a 16-channel correlator and is based on an ARM7TDMI ARM

processor core with very low power consumption. It has a high-performance 32 bit RISC archi-

tecture, uses a high-density 16-bit instruction set. The ARM standard In-Circuit Emulation debug

interface is supported via the JTAG/ICE port of the ATR0635.

The ATR0635 architecture consists of two main buses, the Advanced System Bus (ASB) and

the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It inter-

faces the processor with the on-chip 32-bit memories and the external memories and devices by

means of the External Bus Interface (EBI). The APB is designed for accesses to on-chip periph-

between the ASB and the APB.

An on-chip Peripheral Data Controller (PDC2) transfers data between the on-chip USARTs/SPI

and the on- and off-chip memories without processor intervention. Most importantly, the PDC2

removes the processor interrupt handling overhead and significantly reduces the number of

clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes without

reprogramming the starting address. As a result, the performance of the microcontroller is

increased and the power consumption reduced.

All of the external signals of the on-chip peripherals are under the control of the Parallel I/O Con-

troller (PIO2). The PIO2 Controller can be programmed to insert an input filter on each pin or

generate an interrupt on a signal change. After reset, the user must carefully program the PIO2

Controller in order to define which peripheral signals are connected with off-chip logic.

The ATR0635 features a Programmable Watchdog Timer.

An Advanced Power Management Controller (APMC) allows for the peripherals to be deacti-

vated individually. Automatic master clock gearing reduces power consumption. A Sleep Mode

is available with disabled 23.104 MHz master clock, as well as a Back-up Mode operating

32.768 kHz master clock.

A 32.768 kHz Real Time Clock (RTC), together with a buit-in battery back-up SRAM, allows for

storage of Almanac, Ephemeris, software configurations to make quick hot- and warm starts.

The ATR0635 includes the full high performance firmware (SuperSense), licensed from u-blox

AG, Switzerland. Features of the ROM firmware are described in a software documentation

available from u-blox AG, Switzerland.