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AT90USB646 Datasheet(PDF) 288 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 288 Page - ATMEL Corporation |
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288 / 459 page ![]() 288 7593H–AVR–11/08 ATmega32U6/AT90USB64/128 This bit is inactive (cleared) if the endpoint is an OUT endpoint. • 7 - FLERRE - Flow Error Interrupt Enable Flag Set to enable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent. Clear to disable an endpoint interrupt (EPINTx) when OVERFI or UNDERFI are sent. • 6 - NAKINE - NAK IN Interrupt Enable Bit Set to enable an endpoint interrupt (EPINTx) when NAKINI is set. Clear to disable an endpoint interrupt (EPINTx) when NAKINI is set. • 5 - Reserved The value read from these bits is always 0. Do not set these bits. • 4 - NAKOUTE - NAK OUT Interrupt Enable Bit Set to enable an endpoint interrupt (EPINTx) when NAKOUTI is set. Clear to disable an endpoint interrupt (EPINTx) when NAKOUTI is set. • 3 - RXSTPE - Received SETUP Interrupt Enable Flag Set to enable an endpoint interrupt (EPINTx) when RXSTPI is sent. Clear to disable an endpoint interrupt (EPINTx) when RXSTPI is sent. • 2 - RXOUTE - Received OUT Data Interrupt Enable Flag Set to enable an endpoint interrupt (EPINTx) when RXOUTI is sent. Clear to disable an endpoint interrupt (EPINTx) when RXOUTI is sent. • 1 - STALLEDE - Stalled Interrupt Enable Flag Set to enable an endpoint interrupt (EPINTx) when STALLEDI is sent. Clear to disable an endpoint interrupt (EPINTx) when STALLEDI is sent. • 0 - TXINE - Transmitter Ready Interrupt Enable Flag Set to enable an endpoint interrupt (EPINTx) when TXINI is sent. Clear to disable an endpoint interrupt (EPINTx) when TXINI is sent. • 7-0 - DAT7:0 -Data Bits Set by the software to read/write a byte from/to the endpoint FIFO selected by EPNUM. Bit 7 6 5 4 3 210 FLERRE NAKINE - NAKOUTE RXSTPE RXOUTE STALLEDE TXINE UEIENX Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 765 43210 DAT D7 DAT D6 DAT D5 DAT D4 DAT D3 DAT D2 DAT D1 DAT D0 UEDATX Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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