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LTC2272 Datasheet(PDF) 30 Page - Linear Technology

Part # LTC2272
Description  16-Bit, 80Msps/65Msps Serial Output ADC
PDF  44 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC2272 Datasheet(HTML) 30 Page - Linear Technology

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LTC2273/LTC2272
30
22732f
SYNC
REQUEST?
START
IS ISMODE
ENABLED?
NEGATIVE
DISPARITY?
DATA TRANSMISSION
FLOW (SEE FIGURE 18)
TRANSMIT K28.5
AS CODE GROUP 1
WAIT FOR NEXT
FRAME CLOCK
TRANSMIT K28.5
AS CODE GROUP 2
TRANSMIT K28.5
AS CODE GROUP 1
TRANSMIT D5.6
AS CODE GROUP 2
TRANSMIT K28.5
AS CODE GROUP 1
TRANSMIT D16.2
AS CODE GROUP 2
NO
YES
NO
YES
NO
(DISPARITY NOT OK)
(NEGATIVE DISPARITY)
(NEGATIVE DISPARITY)
(DISPARITY IS OK)
(POSITIVE DISPARITY)
(NEGATIVE DISPARITY)
22732 F15
YES
APPLICATIONS INFORMATION
Figure 15. Initial Synchronization Flow Diagram
Scrambling
To avoid spectral interference from the serial data output,
an optional data scrambler is added between the ADC
data and the 8B/10B encoder to randomize the spectrum
of the serial link. The scrambler is enabled by setting the
SCRAM pin to a high logic level. The polynomial used for
the scrambler is 1 + x14 + x15, which is a pseudo-random
pattern repeating itself every 215–1. Figure 16 illustrates
the LTC2273/LTC2272 implementation of this polynomial
in parallel form.
The scrambled data is converted into two valid 8B/10B
code groups, constituting a complete frame. The 8B/10B
code groups are then serialized and transmitted.
The receiver is required to deserializing the data, decode
the code-groups into octets and descramble them back
to the original octets using the self-aligning descrambler
shown in Figure 17. This descrambler is shown in 16-bit
parallel form, which is an efficient implementation of the
(1 + x14 + x15) polynomial, operating at the frame clock
rate (ADC sample rate).



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