LTC2485CDD datasheet(22/40 Pages) LINER

22 / 40 page

LTC2485

2485fa

For a simple approximation, the source impedance RS

driving an analog input pin (IN+, IN–, REF+ or REF–) can be

considered to form, together with RSW and CEQ (see

Figure 12), a first order passive network with a time con-

stant

τ = (RS + RSW) • CEQ. The converter is able to sample

the input signal with better than 1ppm accuracy if the

sampling period is at least 14 times greater than the input

circuit time constant

τ. The sampling process on the four

input analog pins is quasi-independent so each time con-

stant should be considered by itself and, under worst-case

circumstances, the errors may add.

When using the internal oscillator, the LTC2485’s front-

end switched-capacitor network is clocked at 123kHz

corresponding to an 8.1

µs sampling period. Thus, for

settling errors of less than 1ppm, the driving source

impedance should be chosen such that

τ ≤ 8.1µs/14 =

580ns. When an external oscillator of frequency fEOSC is

used, the sampling period is 2.5/fEOSC and, for a settling

error of less than 1ppm,

τ ≤ 0.178/fEOSC.

Automatic Differential Input Current Cancellation

In applications where the sensor output impedance is low

(up to 10k

Ω with no external bypass capacitor or up to

500

Ω with 0.001µF bypass), complete settling of the input

occurs. In this case, no errors are introduced and direct

digitization of the sensor is possible.

For many applications, the sensor output impedance com-

bined with external bypass capacitors produces RC time

constants much greater than the 580ns required for 1ppm

accuracy. For example, a 10k

Ω bridge driving a 0.1µF

bypass capacitor has a time constant an order of magni-

tude greater than the required maximum. Historically,

settling issues were solved using buffers. These buffers

led to increased noise, reduced DC performance (Offset/

Drift), limited input/output swing (cannot digitize signals

near ground or VCC), added system cost and increased

power. The LTC2485 uses a proprietary switching algo-

rithm that forces the average differential input current to

zero independent of external settling errors. This allows

accurate direct digitization of high impedance sensors

without the need of buffers (see Figures 13 to 15). Addi-

tional errors resulting from mismatched leakage currents

must also be taken into account.

The switching algorithm forces the average input current

on the positive input (IIN+) to be equal to the average input

current on the negative input (IIN–). Over the complete

conversion cycle, the average differential input current

(IIN+ – IIN–) is zero. While the differential input current is

zero, the common mode input current (IIN++ IIN–)/2 is

proportional to the difference between the common mode

input voltage (VINCM) and the common mode reference

voltage (VREFCM).

In applications where the input common mode voltage is

equal to the reference common mode voltage, as in the

case of a balance bridge type application, both the differ-

ential and common mode input current are zero. The

accuracy of the converter is unaffected by settling errors.

Mismatches in source impedances between IN+ and IN–

also do not affect the accuracy.

In applications where the input common mode voltage is

constant but different from the reference common mode

voltage, the differential input current remains zero while

the common mode input current is proportional to the

difference between VINCM and VREFCM. For a reference

common mode of 2.5V and an input common mode of

1.5V, the common mode input current is approximately

0.74

µA (in simultaneous 50Hz/60Hz rejection mode). This

common mode input current has no effect on the accuracy

if the external source impedances tied to IN+ and IN– are

matched. Mismatches in these source impedances lead to

a fixed offset error but do not affect the linearity or full-

scale reading. A 1% mismatch in 1k

Ω source resistances

leads to a 15ppm shift (74

µV) in offset voltage.

In applications where the common mode input voltage

varies as a function of input signal level (single-ended

input, RTDs, half bridges, current sensors, etc.), the

common mode input current varies proportionally with

input voltage. For the case of balanced input impedances,

the common mode input current effects are rejected by the

large CMRR of the LTC2485 leading to little degradation in

accuracy. Mismatches in source impedances lead to gain

errors proportional to the difference between the common

mode input voltage and the common mode reference

voltage. 1% mismatches in 1k

Ω source resistances lead

to worst-case gain errors on the order of 15ppm or 1LSB

(for 1V differences in reference and input common mode

APPLICATIO S I FOR ATIO

LTC2485CDD Datasheet(PDF) 22 Page - Linear Technology

LTC2485CDD Datasheet(HTML) 22 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Datasheet Download

Link URL