LTC3412 datasheet(14/20 Pages) LINER

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LTC3412

3412fb

APPLICATIO S I FOR ATIO

If we set the sum of R2 and R3 to 185k, then the following

equations can be solved:

185

032

The last two equations shown result in the following

values for R2 and R3: R2 = 110k , R3 = 75k. The value of

R1 can now be determined by solving the equation shown

below:

185

1 393

A value of 392k will be selected for R1. Figure 4 shows the

complete schematic for this design example.

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of the

LTC3412. Check the following in your layout.

1. A ground plane is recommended. If a ground plane layer

is not used, the signal and power grounds should be

segregated with all small-signal components returning to

the SGND pin at one point which is then connected to the

PGND pin close to the LTC3412. The exposed pad should

be connected to SGND.

2. Connect the (+) terminal of the input capacitor(s), CIN,

as close as possible to the PVIN pin. This capacitor

provides the AC current into the internal power MOSFETs.

3. Keep the switching node, SW, away from all sensitive

small-signal nodes.

4. Flood all unused areas on all layers with copper. Flood-

ing with copper will reduce the temperature rise of power

components. You can connect the copper areas to any DC

net (PVIN, SVIN, VOUT, PGND, SGND, or any other DC rail

in your system).

5. Connect the VFB pin directly to the feedback resistors.

The resistor divider must be connected between VOUT and

SGND.

Figure 3. LTC3412 Layout Diagram

Top Side

Bottom Side

LTC3412 Datasheet(PDF) 14 Page - Linear Technology