TMP320C40 datasheet(48/62 Pages) TI

48 / 62 page

SMJ320C40, TMP320C40

DIGITAL SIGNAL PROCESSORS

SGUS017H – OCTOBER 1993 – REVISED OCTOBER 2001

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

timing parameters for IIOF3–IIOF0 interrupt response [P = tc(H)] (see Figure 21, Note 7, and

Note 8)

NO.

’320C40-40

’320C40-50

’320C40-60

UNIT

NO.

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

tsu(IIOF-H1L)

Setup time, IIOF3–IIOF0 before H1 low

11*

tw(IIOF)

Interrupt pulse duration to ensure one interrupt seen

(see Note 9)

1.5P

< 2P*

1.5P

< 2P*

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

NOTES:

7. IIOFx is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact

sequence shown occurs; otherwise, an additional delay of one clock cycle can occur.

8. Edge-triggered interrupts require a setup of time (1) and a minimum duration of P. No maximum duration limit exists.

9. Level-triggered interrupts require interrupt pulse duration of at least 1P wide (P = one H1 period) to ensure that the interrupt is seen.

It must be less than 2P wide to ensure that it is responded to only once. Recommended pulse duration is 1.5P.

Reset or

Interrupt

Vector Read

Fetch First

Instruction of

Service

Routine

IIOF3–IIOF0

Pins

IIOF3–IIOF0

Flag

ADDRESS

Data

Vector

Address

First

Instruction

Address

1 (See Note A)

NOTE A: The ’C40 can accept an interrupt from the same source every two H1 clock cycles.

Figure 21. IIOF3–IIOF0 Interrupt Response Timing [P=tc(H)]

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