TMP320C40 datasheet(12/62 Pages) TI

12 / 62 page

SMJ320C40, TMP320C40

DIGITAL SIGNAL PROCESSORS

SGUS017H – OCTOBER 1993 – REVISED OCTOBER 2001

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

SMJ320C40 Signal Descriptions (Continued)

SIGNAL

DESCRIPTION

TYPE†

NAME

DESCRIPTION

TYPE†

NO. OF

PINS

COMMUNICATION PORT 5 INTERFACE (12 PINS)

C5D7–C5D0

I/O

Communication port 5 data bus

CREQ5

I/O

Communication port 5 token-request signal

CACK5

I/O

Communication port 5 token-request-acknowledge signal

CSTRB5

I/O

Communication port 5 data-strobe signal

CRDY5

I/O

Communication port 5 data-ready signal

INTERRUPTS, I/O FLAGS, RESET, TIMER (12 PINS)

IIOF3–IIOF0

I/O

Interrupt and I/O flags

NMI

Nonmaskable interrupt. NMI is sensitive to a low-going edge.

IACK

Interrupt acknowledge

RESET

Reset signal

RESETLOC1–

RESETLOC0

Reset-vector location pins

ROMEN

On-chip ROM enable (0 = disable, 1 = enable)

TCLK0

I/O

Timer 0 pin

TCLK1

I/O

Timer 1 pin

CLOCK (4 PINS)

Crystal pin

X2/CLKIN

Crystal/oscillator pin

H1 clock

H3 clock

POWER AND GROUND (70 PINS)§

CVSS

15§

Ground pins

DVSS

15§

Ground pins

IVSS

6§

Ground pins

DVDD

5-VDC supply pins

GADVDD

3§

5-VDC supply pins

GDDVDD

3§

5-VDC supply pins

LADVDD

3§

5-VDC supply pins

LDDVDD

3§

5-VDC supply pins

SUBS

Substrate pin (tie to ground)

VDDL

5-VDC supply pins

VSSL

Ground pins

† I = input, O = output, Z = high impedance

‡ STRB0, STRB1 and associated signals (R/W1, R/W0, PAGE0, PAGE1, etc.) are effective over the address ranges defined by the

STRB ACTIVE bits.

§ HFH package has additional power and ground pins to reduce noise problems.

signal descriptions (continued)

TMP320C40 Datasheet(PDF) 12 Page - Texas Instruments

TMP320C40 Datasheet(HTML) 12 Page - Texas Instruments

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