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TMP320C40 Datasheet(PDF) 49 Page - Texas Instruments |
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TMP320C40 Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 62 page ![]() SMJ320C40, TMP320C40 DIGITAL SIGNAL PROCESSORS SGUS017H – OCTOBER 1993 – REVISED OCTOBER 2001 49 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 timing parameters for IACK (see Note 10 and Figure 22) NO. ’320C40-40 ’320C40-50 ’320C40-60 UNIT NO. MIN MAX MIN MAX UNIT 1 td(H1H-IACKL) Delay time, H1 high to IACK low 9 7 ns 2 td(H1L-IACKH) Delay time, H1 low to IACK high during first cycle of IACK instruction data read 9 7 ns NOTE 10: The IACK output is active for the entire duration of the bus cycle and, therefore, is extended if the bus cycle utilizes wait states. H3 H1 IACK ADDRESS DATA 12 Fetch IACK Instruction IACK Data Read Decode IACK Instruction Execute IACK Instruction Figure 22. IACK Timing |
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