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TL16C552AMFN Datasheet(PDF) 14 Page - Texas Instruments |
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TL16C552AMFN Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 39 page  TL16C552A, TL16C552AM DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH FIFO SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION Trigger Interrupt (FCR6, 7=0, 0) Active Parity Data Bits 5 – 8 Stop Start Active tpd7 td9 SIN Sample CLK IOR (RD LSR) LSI Interrupt IOR (RD RBR) (FIFO at or above trigger level) (FIFO below trigger level) tpd7 50% 50% 50% 50% 50% 50% Figure 10. Receiver FIFO First Byte (Sets RDR) Waveforms Active Active Top Byte of FIFO IOR (RD LSR) CLK Sample SIN Active Time Out or Trigger Level Interrupt LSI Interrupt IOR (RD RBR) (FIFO at or above trigger level) (FIFO below trigger level) Previous Byte Read From FIFO Stop td9 (see Note A) tpd7 td9 tpd7 50% 50% 50% 50% 50% 50% 50% NOTE A: This is the reading of the last byte in the FIFO. Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms |
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