TL16C552A, TL16C552AM

DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

25

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

line printer port (continued)

Table 6 summarizes the configuration of the PD port based on the combinations of the logic level on the

PEMD terminal and the value of the direction control bit (DIR).

Table 6. Extended Mode and Direction Control Bit Combinations

PEMD

DIR

PD0 – PD7 FUNCTION

L

X

PC/AT mode – output

H

0

PS/2 mode – output

H

1

PS/2 mode – input

register 1 read line printer status register

The line printer status (LPS) register is a read-only register that contains interrupt and printer status of the LPT

connector terminals. Table 7 (in the default column) shows the values of each bit after reset in the case of the

printer being disconnected from the port.

Table 7. LPS Register Bit Description

BIT

DESCRIPTION

DEFAULT

0

Reserved

1

1

Reserved

1

2

PRINT

1

3

ERR

†

4

SLCT

†

5

PE

†

6

ACK

†

7

BSY

†

† Outputs are dependent upon device inputs.

printer has acknowledged the previous transfer with an ACK handshake (if bit 4 of the control register is set).

The bit is cleared on the active-to-inactive transition of the ACK signal. This bit is set after a read of the status

port.