TL16C552AMFN datasheet(22/39 Pages) TI

22 / 39 page

TL16C552A, TL16C552AM

DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

interrupt enable register (IER) (continued)

D Bit 1: When IER1 is set, the transmitter holding register empty interrupt is enabled.

D Bit 2: When IER2 is set, the receiver line status interrupt is enabled.

D Bit 3: When IER3 is set, the modem status interrupt is enabled.

D Bits 4 – 7: IER4 through IER7 are cleared.

In order to minimize software overhead during data character transfers, the serial channel prioritizes interrupts

into four levels. The four levels of interrupt conditions are as follows:

D Priority 1 – Receiver line status (highest priority)

D Priority 2 – Receiver data ready or receiver character time out

D Priority 3 –Transmitter holding register empty

D Priority 4–Modem status (lowest priority)

Information indicating that a prioritized interrupt is pending and the type of interrupt is stored in the IIR. The IIR

indicates the highest priority interrupt pending. The contents of the IIR are indicated in Table 5.

Table 5. Interrupt Control Functions

INTERRUPT

IDENTIFICATION

INTERRUPT SET AND RESET FUNCTIONS

BIT 3

BIT 2

BIT 1

BIT 0

PRIORITY

LEVEL

INTERRUPT TYPE

INTERRUPT SOURCE

INTERRUPT RESET

CONTROL

None

First

Receiver line status

OE, PE, FE, or BI

LSR read

Second

Received data available

Receiver data available or trigger level

reached

RBR read until FIFO

drops below the

trigger level

Second

Character time-out

indicator

No characters have been removed from or

input to the receiver FIFO during the last

four character times and there is at least

one character in it during this time.

RBR read

Third

THRE

IIR read if THRE is

the interrupt source

or THR write

Fourth

Modem status

CTS, DSR, RI, or DCD

MSR read

D Bit 0: IIR0 indicates whether an interrupt is pending. When IIR0 is cleared, an interrupt is pending.

D Bits 1 and 2: IIR1 and IIR2 identify the highest priority interrupt pending, as indicated in Table 5.

D Bit 3: IIR3 is always cleared in TL16C450 mode. This bit is set along with bit 2 in FIFO mode and when a

trigger change level interrupt is pending.

D Bits 4 and 5: IIR4 and IIR5 are always cleared.

D Bits 6 and 7: IIR6 and IIR7 are set when FCR0 = 1.

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