TL16C552A, TL16C552AM

DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

32

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

parallel port registers

The TL16C552A parallel port can connect the device to a Centronic-style printer interface. When chip select 2

(CS2) is low, the parallel port is selected. Table 12 shows the registers associated with this parallel port. The

read or write function of the register is controlled by the state of the read (IOR) and write (IOW) terminals as

shown. The read data register allows the microprocessor to read the information on the parallel bus.

The read status register allows the microprocessor to read the status of the printer in the six most significant

bits. The status bits are printer busy BSY, acknowledge (ACK) (a handshake function), paper empty (PE), printer

selected (SLCT), error (ERR), and printer interrupt (PRINT). The read control register allows the state of the

control lines to be read. The write control register sets the state of the control lines. They are direction (DIR),

interrupt enable (INT2 EN), select in (SLIN), initialize the printer (INIT), autofeed the paper (AFD), and strobe

(STB), which informs the printer of the presence of a valid byte on the parallel bus. The write data register allows

the microprocessor to write a byte to the parallel bus. The parallel port is completely compatible with the parallel

port implementation used in the IBM serial parallel adapter.

Table 12. Parallel Port Registers

REGISTER

REGISTER BITS

REGISTER

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Read data

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

Read status

BSY

ACK

PE

SLCT

ERR

PRINT

1

1

Read control

0

0

PEMD

• DIR INT2 EN

SLIN

INIT

AFD

STB

Write data

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

Write control

0

0

DIR

INT2 EN

SLIN

INIT

AFD

STB

Table 13. Parallel Port Register Select

CONTROL PINS

REGISTER SELECTED

IOR

IOW

CS2

A1

A0

REGISTER SELECTED

L

H

L

L

L

Read data

L

H

L

L

H

Read status

L

H

L

H

L

Read control

L

H

L

H

H

Invalid

H

L

L

L

L

Write data

H

L

L

L

H

Invalid

H

L

L

H

L

Write control

H

L

L

H

H

Invalid

programmable baud rate generator

The ACE serial channel contains a programmable baud rate generator (BRG) that divides the clock (dc to

# = clock

÷ (baud rate x 16)], referred to in this document as RCLK. Two 8-bit divisor latch registers store the

divisor in a 16-bit binary format. These divisor latch registers must be loaded during initialization. Upon loading

either of the divisor latches, a 16-bit baud counter is immediately loaded. This prevents long counts on initial

load. The BRG can use any of three different popular frequencies to provide standard baud rates. These

frequencies are 1.8432 MHz, 3.072 MHz, and 8 MHz. With these frequencies, standard bit rates from 50 to

512 kbps are available. Tables 14, 15, 16, and 17 illustrate the divisors needed to obtain standard rates using

these three frequencies.