TL16C552A, TL16C552AM

DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

24

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

line control register (LCR) (continued)

LCR

7

LCR

6

LCR

5

LCR

4

LCR

3

LCR

2

LCR

1

LCR

0

Line Control Register

Word Length

Select

Stop Bit

Select

Parity Enable

Even Parity

Select

Stick Parity

Break Control

Divisor Latch

Access Bit

0 0 = 5 Data Bits

0 1 = 6 Data Bits

1 0 = 7 Data Bits

1 1 = 8 Data Bits

0 = 1 Stop Bits

1 = 1.5 Stop Bits if 5 Data Bits Selected

2 Stop Bits if 6, 7, 8 Data Bits Selected

0 = Parity Disabled

1 = Parity Enabled

0 = Odd Parity

1 = Even Parity

0 = Stick Parity Disabled

1 = Stick Parity Enabled

0 = Break Disabled

1 = Break Enabled

0 = Access Receiver Buffer

1 = Access Divisor Latches

Figure 19. Line Control Register Contents

line printer port

The line printer port contains the functionality of the port included in the TL16C452 but offers a hardware

programmable extended mode controlled by the printer enhancement mode (PE) terminal. This enhancement

is the addition of a direction control bit and an interrupt status bit.

register 0 line printer data register

The line printer (LPT) port is either output only or bidirectional depending on the state of the extended mode

terminal and data direction control bits.

Compatibility mode (PEMD = L)

Reads to the LPT data register and returns the last data that was written to the port. Write operations

immediately output data to PD0 – PD7.

Extended mode (PEMD = H)

Read operations return either the data last written to the LPT data register when the direction bit is cleared or

return the data that is present on PD0 – PD7 when the direction is set to read. Write operations to the LPT

data register latch data into the output register; however, they only drive the LPT port when the direction bit is

cleared.