TL16C552A, TL16C552AM

DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH FIFO

SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999

29

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

master reset (continued)

Table 10. RESET Effects on Registers and Signals

REGISTER/SIGNAL

RESET CONTROL

RESET

Interrupt enable register

Reset

All bits cleared (0 – 3 forced and 4 – 7 permanent)

Interrupt identification register

Reset

Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits 4 – 5 are permanently

Interrupt identification register

Reset

,

,,,,

,

y

cleared.

Line control register

Reset

All bits are cleared.

Modem control register

Reset

All bits are cleared (5 – 7 permanently).

FIFO control register

Reset

All bits are cleared.

Line status register

Reset

All bits are cleared, except bits 5 and 6 are set.

Modem status register

Reset

Bits 0 – 3 are cleared, bits 4 – 7 input signal.

SOUT

Reset

High

Interrupt (RCVR errors)

Read LSR/Reset

Low

Interrupt (receiver data ready)

Read RBR/Reset

Low

Interrupt (THRE)

Read IIR/Write THR/Reset

Low

Interrupt (modem status changes)

Read MSR/Reset

Low

OUT2

Reset

High

RTS

Reset

High

DTR

Reset

High

OUT1

Reset

High

modem control register (MCR)

The MCR controls the interface with the modem or data set as described in Figure 20. MCR can be written to

and read from. The RTS and DTR outputs are directly controlled by their control bits in this register. A high input

asserts a low signal (active) at the output terminals. The MCR bits are defined in the following bulleted list.

high. The DTR output of the serial channel can be input into an inverting line driver in order to obtain the

proper polarity input at the modem or data set.

high. The RTS output of the serial channel can be input into an inverting line driver to obtain the proper

polarity input at the modem or data set.

SOUT is set to the marking (high) state and the SIN is disconnected. The output of the transmitter shift

register is looped back into the receiver shift register input. The four modem control inputs (CTS, DSR, DCD,

and RI) are disconnected. The modem control outputs (DTR, RTS, OUT1, and OUT2) are internally

connected to the four modem control inputs. The modem control output terminals are forced to their inactive

(high) state on the TL16C552A. In the diagnostic mode, data transmitted is immediately received. This

allows the processor to verify the transmit and receive data paths of the selected serial channel. Interrupt

control is fully operational; however, interrupts are generated by controlling the lower four MCR bits

internally. Interrupts are not generated by activity on the external terminals represented by those four bits.