TMS320C240 datasheet(39/105 Pages) TI

39 / 105 page

TMS320C240, TMS320F240

DSP CONTROLLERS

SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

flash control mode register (continued)

After completing all the necessary reads and/or writes to the control registers, an IN xxxx, FF0Fh instruction

(with dummy data) is executed to place the flash array back in array access mode. After executing the

IN xxxx, FF0Fh

instruction, the flash array is accessed in the decoded space and the flash registers are

not available. Switching between the register access mode and the array access mode is done by issuing the

and OUT instructions. The memory content in these instructions (denoted by xxxx) is not relevant. Refer to

the

TMS320F20x/F24x DSPs Embedded Flash Memory Technical Reference (literature number SPRU282) for

a detailed description of the flash programming algorithms.

peripherals

The integrated peripherals of the TMS320x240 are described in the following subsections:

D External memory interface

D Event manager (EV)

D Dual analog-to-digital converter (ADC)

D Serial peripheral interface (SPI)

D Serial communications interface (SCI)

D Watchdog timer (WD)

external memory interface

The TMS320x240 can address up to 64K words

× 16 bits of memory or registers in each of the program, data,

and I/O spaces. On-chip memory, when enabled, removes some of this off-chip range. In data space, the high

32K words can be mapped dynamically as either local or global using the GREG register. A data-memory

access mapped as global asserts BR low (with timing similar to the address bus).

The CPU of the TMS320x240 schedules a program fetch, data read, and data write on the same machine cycle.

This is because, from on-chip memory, the CPU can execute all three of these operations in the same cycle.

However, the external interface multiplexes the internal buses to one address and one data bus. The external

interface sequences these operations to complete the data write first, then the data read, and finally the program

read.

The ’x240 supports a wide range of system interfacing requirements. Program, data, and I/O address spaces

provide interface to memory and I/O, maximizing system throughput. The full 16-bit address and data bus, along

with the PS, DS, and IS space-select signals allow addressing of 64K 16-bit words in program and I/O space.

Due to the on-chip peripherals, external data space is addressable to 32K 16-bit words.

I/O design is simplified by having I/O treated the same way as memory. I/O devices are mapped into the I/O

address space using the processor’s external address and data buses in the same manner as memory-mapped

devices.

The ’x240 external parallel interface provides control signals to facilitate interfacing to the device. The R/W

output signal is provided to indicate whether the current cycle is a read or a write. The STRB output signal

provides a timing reference for all external cycles.

Interface to memory and I/O devices of varying speeds is accomplished by using the READY input. When

transactions are made with slower devices, the ’x240 processor waits until the other device completes its

function and signals the processor by way of the READY input. Once a ready indication is provided from the

external device, execution continues. On the ’x240 device, the READY input must be driven (active high) to

complete reads or writes to internal data I/O-memory-mapped registers and all external addresses.

TMS320C240 Datasheet(PDF) 39 Page - Texas Instruments

TMS320C240 Datasheet(HTML) 39 Page - Texas Instruments

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