TMS320C240 datasheet(15/105 Pages) TI

15 / 105 page

TMS320C240, TMS320F240

DSP CONTROLLERS

SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

peripheral memory map

The TMS320x240 system and peripheral control register frame contains all the data, status, and control bits

to operate the system and peripheral modules on the device (excluding the event manager).

Global-Memory Allocation

0000

0003

0004

0005

0000

Memory-Mapped Registers

and Reserved

005F

0060

On-Chip DARAM B2

02FF

0300

01FF

0200

03FF

On-Chip

DARAM B1

0400

Reserved

73FF

Peripheral Frame 1

7400

77FF

7800

External

FFFF

7000 – 700F

Reserved

0007

Emulation Registers

and Reserved

Peripheral Frame 2

Reserved

On-Chip DARAM

B0 (CNF = 0)

Reserved (CNF = 1)

Interrupt-Mask Register

Illegal

System Configuration and

Control Registers

Watchdog Timer and

PLL Control Registers

Illegal

Digital-I/O Control Registers

Illegal

Reserved

Interrupt Mask, Vector and

Flag Registers

0006

005F

007F

0080

07FF

7000

743F

7440

7010 – 701F

7020 – 702F

7030 – 703F

7040 – 704F

7050 – 705F

7060 – 706F

7070 – 707F

7080 – 708F

7090 – 709F

7400 – 740C

7411 – 741C

7420 – 7426

7427 – 742B

742C – 7434

7435 – 743F

Interrupt Flag Register

SPI

SCI

Illegal

External-Interrupt Registers

ADC

General-Purpose

Timer Registers

Capture & QEP Registers

Compare, PWM, and

Deadband Registers

Reserved

7FFF

8000

Illegal

0800

6FFF

Illegal

Hex

70A0 – 73FF

Reserved

741D – 741F

740D – 7410

Figure 2. Peripheral Memory Map

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