TMS320C240 datasheet(21/105 Pages) TI

21 / 105 page

TMS320C240, TMS320F240

DSP CONTROLLERS

SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

hardware-generated interrupts (continued)

DSP Core

INTC INTB

INTA

Address

Lines 5–1

INT6 INT5 INT4 INT3 INT2 INT1 NMI

Address

Lines 5–1

System Module

Event Manager

IACK

INT6 INT5 INT4 INT3 INT2 INT1 NMI

IACK

Figure 5. DSP Interrupt Structure

At the level of the system module and the event manager, each of the maskable interrupt lines (INT1–INT6) is

connected to multiple maskable interrupt sources. Sources connected to interrupt line INT1 are called Level 1

interrupts; sources connected to interrupt line INT2 are called Level 2 interrupts; and so on. For each interrupt

line, the multiple sources also have a set priority ranking. The source with the highest priority has its interrupt

request responded to by the DSP core first.

Figure 6 shows the sources and priority ranking for the interrupts controlled by the system module. For each

interrupt chain, the interrupt source of highest priority is at the top. Priority decreases from the top of the chain

to the bottom. Figure 7 shows the interrupt sources and priority ranking for the event manager interrupts.

TMS320C240 Datasheet(PDF) 21 Page - Texas Instruments