TMS320C240 datasheet(94/105 Pages) TI

94 / 105 page

TMS320C240, TMS320F240

DSP CONTROLLERS

SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

operating characteristics over recommended operating condition ranges†

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

VCCA =5 5V

converting

ICCA

Analog supply current

VCCA = 5.5 V

non-converting

ICCA

Analog su

ly current

VCCA = VREFHI = 5.5 V

PLL or OSC power

down

Iref

Input charge current, VREFHI or VREFLO

VCCA = VCCD = VREFHI = 5.5 V, VREFLO = 0 V

C i

Analog input capacitance

Typical capacitive load on

non-sampling

Cai

Analog input capacitance

analog input pin

sampling

ZAI

Analog input source impedance

Analog input source impedance for conversions to

remain within specifications.

Ω

EDNL

Differential nonlinearity error

Difference between the actual step width and the ideal

value

– 1

1.5

LSB

EINL

Integral nonlinearity error

Maximum deviation from the best straight line through

the ADC transfer characteristics, excluding the

quantization error

"1.5

LSB

td(PU)

Delay time, power-up to ADC valid

Time to stabilize analog stage after power-up

† Absolute resolution=4.89mV.AtVREFHI=5VandVREFLO=0V,thisisoneLSB.AsVREFHIdecreases,VREFLOincreases,orboth,theLSBsizes

decrease. Therefore, the absolute accuracy and differential/integral linearity errors in terms of LSBs increase.

The ADC module allows complete freedom in the design of the sources for the analog inputs. The period of the

sample time is independent of the source impedance. The sample-and-hold period occurs in the first half-period

of the ADC clock after the ADCIMSTART bit or the ADCSOC bit of the ADC control register 1 (ADCTRL1, bits 13

and 0, respectively) is set to 1. The conversion then occurs during the next six ADC clock cycles. The digital

result registers are updated on the next ADC clock cycle once the conversion is completed.

ADC input pin circuit

One of the most common A/D application errors is inappropriate source impedance. In practice, minimum

source impedance should be used to limit the error as well as minimize the required sampling time; however,

the source impedance must be smaller than ZAI. A typical ADC input pin circuit is shown in Figure 47.

VIN

Requiv

VAI (to ADCINx input)

R1 = 9 k

Ω typical

Figure 47. Typical ADC Input Pin Circuit

TMS320C240 Datasheet(PDF) 94 Page - Texas Instruments

TMS320C240 Datasheet(HTML) 94 Page - Texas Instruments

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