TMS320C240 datasheet(13/105 Pages) TI

13 / 105 page

TMS320C240, TMS320F240

DSP CONTROLLERS

SPRS042D – OCTOBER 1996 – REVISED NOVEMBER 1998

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

description (continued)

Table 1. Characteristics of the ’x240 DSP Controllers

ON-CHIP MEMORY (WORDS)

POWER

CYCLE

PACKAGE

TMS320x240

DEVICES

RAM

ROM

FLASH

EEPROM

POWER

SUPPLY

(V)

CYCLE

TIME

(ns)

PACKAGE

TYPE

PIN COUNT

DATA

DATA / PROG

PROG

(V)

(ns)

PIN COUNT

TMS320C240

288

256

16K

–

PQ 132–P

TMS320F240

288

256

–

16K

PQ 132–P

architectural overview

The functional block diagram provides a high-level description of each component in the ’x240 DSP controller.

The TMS320x240 devices are composed of three main functional units: a ’C2xx DSP core, internal memory,

and peripherals. In addition to these three functional units, there are several system-level features of the ’x240

that are distributed. These system features include the memory map, device reset, interrupts, digital

input / output (I / O), clock generation, and low-power operation.

system-level functions

device memory map

The TMS320x240 implements three separate address spaces for program memory, data memory, and I / O.

Each space accommodates a total of 64K 16-bit words. Within the 64K words of data space, the 256 to

32K words at the top of the address range can be defined to be external global memory in increments of powers

of two, as specified by the contents of the global memory allocation register (GREG). Access to global memory

is arbitrated using the global memory bus request (BR) signal.

On the ’x240, the first 96 (0 – 5Fh) data memory locations are either allocated for memory-mapped registers or

are reserved. This memory-mapped register space contains various control and status registers including those

for the CPU.

All the on-chip peripherals of the ’x240 device are mapped into data memory space. Access to these registers

is made by the CPU instructions addressing their data-memory locations. Figure 1 shows the memory map.

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