TMS320VC5420 datasheet(68/77 Pages) TI

68 / 77 page

TMS320VC5420

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS080C – MARCH 1999 – REVISED APRIL 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

HPI16 timing (continued)

timing requirements [H = 0.5tc(CO)] (see Note 1 and Figure 35 – Figure 42)

MIN

MAX

UNIT

tsu(HBV-DSL)

Setup time, HAD valid before DS falling edge†‡

th(DSL-HBV)

Hold time, HAD valid after DS falling edge†‡

tsu(HBV-HSL)

Setup time, HAD valid before HAS falling edge†

th(HSL-HBV)

Hold time, HAD valid after HAS falling edge†

tsu(HAV-DSH)

Setup time, address valid before DS rising edge (nonmultiplexed write)

tsu(HAV-DSL)

Setup time, address valid before DS falling edge (nonmultiplexed mode)‡

–4H – 5

th(DSH-HAV)

Hold time, address valid after DS rising edge (nonmultiplexed mode)‡

tsu(HSL-DSL)

Setup time, HAS low before DS falling edge‡

th(HSL-DSL)

Hold time, HAS low after DS falling edge‡

tw(DSL)

Pulse duration, DS low‡

tw(DSH)

Pulse duration, DS high‡

Nonmultiplexed or multiplexed mode

Reads

12H

Nonmulti lexed or multi lexed mode

(no increment) with no DMA activity.

Writes

14H

Cycle time, DS rising edge to next DS

Nonmultiplexed or multiplexed mode

Reads

18H

Cycle time, DS rising edge to next DS

rising edge‡

Nonmulti lexed or multi lexed mode

(no increment) with 16-bit DMA activity.

Writes

20H

Nonmultiplexed or multiplexed mode

Reads

26H

Nonmulti lexed or multi lexed mode

(no increment) with 32-bit DMA activity.

Writes

28H

tc(DSH-DSH)

Cycle time, DS rising edge to next DS

‡

Multiplexed (autoincrement) with no DMA

activity.

12H

rising edge‡

(In autoincrement mode WRITE tim-

Multiplexed (autoincrement) with 16-bit DMA

activity.

18H

(In autoincrement mode, WRITE tim-

ings are the same as READ timings.)

Multiplexed (autoincrement) with 32-bit DMA

activity.

26H

Cycle time, DS rising edge to next DS rising edge writes to DSPINT and HINT

tsu(HDV-DSH)

Setup time, HD valid before DS rising edge‡

th(DSH-HDV)W

Hold time, HD valid after DS rising edge, write‡

tsu(SELV-DSL)

Setup time, SELA/B valid before DS falling edge‡

th(DSH-SELV)

Hold time, SELA/B valid after DS Rising edge‡

† HAD stands for HCNTL0, HCNTL1, and HR/W.

‡ DS refers to the logical OR of HCS and HDS.

TMS320VC5420 Datasheet(PDF) 68 Page - Texas Instruments

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